Non-volatile memory system using a plurality of mapping units and operating method thereof

Patent metadata

Field	Value
Publication number	US-10466938-B2
Application number	US-201615157395-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	Aug 18, 2015
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A method of operating a non-volatile memory system, the method comprising: receiving an access request from a host; generating internal requests by processing the access request by a first central processing unit (CPU) according to a first mapping unit having a first size; and accessing a memory by processing the internal requests by a second CPU according to a second mapping unit having a second size; wherein the first size is different from the second size.

First claim

What is claimed is:

1. A method of operating a non-volatile memory system, the method comprising:
receiving an access request from a host;
generating internal requests by processing the access request by a first central processing unit (CPU) according to a first mapping unit having a first size, wherein each of the internal requests comprises a request for data having a same size of the first size, and the first CPU is one of at least one first CPU; and
accessing a memory by processing the internal requests by a second CPU according to a second mapping unit having a second size, wherein the second CPU is one of at least one second CPU,
wherein the first size is different from the second size, and the first size is larger than the second size when a number of the at least one first CPU is smaller than a number of the at least one of second CPU.

2. The method of claim 1 , wherein:
the second CPU is one of a plurality of second CPUs; and
the processing of the internal requests comprises processing the internal requests by the second CPUs according to the second mapping unit.

3. The method of claim 2 , wherein:
the first CPU is one of a plurality of first CPUs; and
the processing of the access request by the first CPUs according to the first mapping unit.

4. The method of claim 1 , wherein:
a data processing speed of the first CPU is faster than that of the second CPU.

5. The method of claim 1 ,
wherein the generating of the internal requests further comprises:
dividing the access request into a plurality of internal requests; and
for each of the internal requests, generating a first logical address corresponding to the internal request.

6. The method of claim 5 , wherein the accessing of the memory further comprises:
generating, based on the first logical address, a plurality of second logical addresses each indicating a logical location of data corresponding to the second size; and
for each of the second logical addresses:
converting the second logical address into a physical address; and
accessing data by providing the physical address to the memory.

7. The method of claim 1 , wherein:
the memory comprises memory cell arrays;
each of the memory cell arrays comprises at least one block;
each of the blocks comprises a plurality of pages;
the first size is equal to M times a page size of each of the pages;
the second size is equal to the page size of each of the pages; and
M is an integer of 2 or greater.

8. The method of claim 1 , wherein:
an operating speed of the at least one first CPU is equal to that of the at least one second CPU;
a ratio of a number of the at least one first CPU and a number of the at least one second CPU is N;
N is an integer of 2 or greater; and
the first size is equal to N times the second size.

9. The method of claim 1 , wherein:
an operating speed of the at least one first CPU is A times faster than that of the at least one second CPU;
a ratio of a number of the at least one first CPU and a number of the at least one second CPU is A*N;
the first size is equal to N times the second size; and
each of A and N is an integer of 2 or greater.

10. The method of claim 1 , wherein:
the second CPU is one of a plurality of second CPUs; and
the size of the second mapping unit of at least one of the second CPUs is different from the size of the second mapping unit of at least one other one of the second CPUs.

11. A method of operating a non-volatile memory system, the method comprising:
receiving an access request by the non-volatile memory system;
generating internal requests by processing the access request according to a first mapping unit having a first size, wherein each of the internal requests comprises a request for data having a same size of the first size;
generating a first logical address indicating a logical location of data corresponding to the internal requests;
generating a command by processing the internal requests according to a second mapping unit having a second size;
generating, based on the first logical address, a second logical address indicating a logical location of data corresponding to the second size;
converting the second logical address into a physical address based on an address mapping table; and
accessing data according to the command and the physical address.

12. The method of claim 11 , wherein:
generating of the internal requests further comprises generating the internal requests by a host interface layer executing on a central processing unit (CPU); and
generating of the command further comprises generating the command by a flash translation layer executing on the CPU.

13. The method of claim 11 , wherein:
generating of the internal requests further comprises generating the internal requests by a first CPU executing a host interface operation according to the first mapping unit, and
generating of the command further comprises generating the command by a second CPU accessing a memory according to the second mapping unit.

14. A method of operating a non-volatile memory system, the method comprising:
receiving an access request from a host;
dividing the access request into at least one internal request according to a first mapping unit, wherein at least one internal request each comprises a request for data having a same size of the first mapping unit;
generating at least one command by reorganizing each of the at least one internal request according to a second mapping unit combining a first one of the internal requests and a portion of a second one of the internal requests into a command; and
accessing a memory with the at least one command,
wherein a size of the first mapping unit is different from a size of the second mapping unit.

15. The method of claim 14 ,
wherein reorganizing each of the at least one internal request comprises dividing each internal request into N commands, each command associated with 1/N of data of the associated internal request and N is an integer of 2 or greater.

16. The method of claim 14 ,
wherein reorganizing each of the at least one internal request further comprises combining a third one of the internal requests and another portion of the second one of the internal requests into a command.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Dong-Young
• Kim Jae-Sub

Classifications

• G06F3/0688 Primary

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0626

  Reducing size or complexity of storage systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title