Memory system with latency distribution optimization and an operating method thereof

Patent metadata

Field	Value
Publication number	US-10416897-B2
Application number	US-201715839244-A
Country	US
Kind code	B2
Filing date	Dec 12, 2017
Priority date	Mar 27, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.

First claim

What is claimed is:

1. A memory system comprising:
a central processing unit (CPU) including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores;
a PCIe link coupled with the CPU, wherein the PCIe link includes a PCIe switch and a plurality of memory devices; wherein
the plurality of memory devices are coupled to the host CPU cores through respective sets of workload threads and interrupt handlers, the workload threads and interrupt handlers are distributed among the host CPU cores, the workload threads have priority of execution with respect to the interrupt handlers, the host CPU cores are isolated for isolated execution of the workload threads and interrupt handlers, and the workload threads and interrupt handlers in each set are executed at the corresponding host CPU core.

2. The memory system recited in claim 1 wherein the workload threads and interrupt handlers are evenly distributed among the host CPU cores.

3. The memory system recited in claim 2 wherein the evenly distributed workload threads and interrupt handlers are a total number of the plurality of memory devices divided by a total number of the host CPU cores.

4. The memory system recited in claim 3 wherein the total number of the host CPU cores is a total number of the multiple CPU cores subtracted by a total number of the reserved CPU cores.

5. The memory system recited in claim 1 wherein the optimized workload threads and interrupt handlers includes a prioritized workload/application with an initial value of the highest system value.

6. The memory system recited in claim 1 wherein the host CPU cores are isolated from idle state.

7. The memory system recited in claim 1 wherein the plurality of memory devices coupled to the host CPU cores includes the plurality of memory devices allocated to the host CPU cores, respectively.

8. The memory system recited in claim 7 wherein the workload threads and interrupt handlers are distributed among the CPU cores by assigning the workload threads and interrupt handlers to the CPU cores in an order based on identification numbers of the CPU cores.

9. An operating method of a memory system comprising:
providing a central processing unit (CPU) including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores;
coupling a PCIe link with the CPU, wherein the PCIe link includes a PCIe switch and a plurality of memory devices;
coupling the plurality of memory devices with the host CPU cores through respective sets of workload threads and interrupt handlers;
distributing the workload threads and interrupt handlers among the host CPU cores;
assigning a higher priority of execution to the workload threads with respect to the interrupt handlers;
isolating the host CPU cores for isolated execution of the workloads threads and interrupt handlers; and
executing each set of the workload threads and interrupt handlers at the corresponding host CPU core.

10. The method recited in claim 9 wherein the workload threads and interrupt handlers are evenly distributed among the host CPU cores.

11. The method recited in claim 10 wherein the evenly distributed workload threads and interrupt handlers are a total number of the plurality of memory devices divided by a total number of the host CPU cores.

12. The method recited in claim 11 wherein the total number of the host CPU cores is a total number of the multiple CPU cores subtracted by a total number of the reserved CPU cores.

13. The method recited in claim 9 wherein the optimized workload threads and interrupt handlers includes a prioritized workload/application with an initial value of the highest system value.

14. The method recited in claim 9 wherein the host CPU cores are isolated from idle state.

15. The method recited in claim 9 wherein the plurality of memory devices coupled with the host CPU cores includes the plurality of memory devices allocated the host CPU cores, respectively.

16. The method recited in claim 15 wherein the distributing comprises assigning the workload threads and interrupt handlers to the CPU cores in an order based on identification numbers of the CPU cores.

Assignees

• Sk Hynix Inc

Inventors

• Jin Young Tack
• Ahn Sungjoon
• Shin Seong Won

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title

• G06F13/1663 Primary

  Access to shared memory · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title