Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor

Patent metadata

Field	Value
Publication number	US-10042750-B2
Application number	US-201313911797-A
Country	US
Kind code	B2
Filing date	Jun 6, 2013
Priority date	Mar 15, 2013
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

First claim

What is claimed is:

1. An apparatus, comprising:
a processing unit configured to run an operating system, wherein the operating system is a memory management hypervisor (MATH) operating system, wherein the MMH operating system provides memory management threads (MMT) configured to manage the memory, wherein the MMH operating system is configured to support a guest operating system run on the processing unit;
a memory coupled to the processing unit, the memory configured to communicate with the processing unit via a memory bus, wherein the memory includes a first memory controller configured to access at least one of a volatile memory or a non-volatile memory; and
an adaptive memory controller configured to receive monitored statistical data from the first memory controller and from the processing unit, wherein the adaptive memory controller is configured to manage the memory based on the monitored statistical data, wherein the adaptive memory controller comprises a memory management processor (MMP) configured to run the MMT, wherein the MMP running the MMT is configured to manage the memory based on the monitored statistical data, wherein the MMP is configured to at least one of:
change a frequency of a portion of the at least one of the non-volatile memory or the volatile memory;
change a refresh period of a portion of the volatile memory;
perform a memory scrub of a portion of the at least one of the non-volatile memory or the volatile memory; or
change a multi-level cell mode of a portion of the at least one of the non-volatile memory or the volatile memory.

2. The apparatus of claim 1 , wherein the MMP comprises a cache and a direct-memory access (DMA) engine, Wherein the DMA engine is configured communicate with the memory.

3. The apparatus of claim 2 , wherein the processing unit includes a cache and the cache of the MMP is coupled to the cache of the processing unit via a common bus.

4. The apparatus of claim 1 , wherein the processing unit is configured to execute the MMH operating system using a first instruction set, and wherein the MMP is configured to execute the MMH operating system using a second instruction set.

5. The apparatus of claim 1 , wherein the memory comprises both a non-volatile memory and a volatile memory.

6. The apparatus of claim 5 , wherein the at least one of the non-volatile memory or the volatile memory is a multi-channel memory.

7. The apparatus of claim 5 , wherein the MMP running the MMT being further configured to change address mapping of a portion of the at least one of the non-volatile memory or the volatile memory.

8. The apparatus of claim 1 , wherein the MMP running the MMT being configured to manage the memory comprises the MMP running the MMT being configured to manage migration of information in the memory.

9. The apparatus of claim 8 , wherein the MMP running the MMT being configured to manage migration of information comprises the MMP running the MMT being configured to provide memory commands to a memory controller instructing the memory controller to move blocks of information in the memory.

10. The apparatus of claim 1 , wherein the MMP is configured to am the MMT to determine when to reconfigure the memory based on the monitored statistical data.

11. The apparatus of claim 1 , wherein the MMP is configured to nm the MMT to determine how to reconfigure the memory based on monitored statistical data.

12. The apparatus of claim 1 , wherein the MMP is configured to run the MMT to map information using an intermediate information depth map.

13. The apparatus of claim 1 , wherein the adaptive memory controller further comprises a performance management unit (PMU) configured to monitor the monitored statistical data, the PMU further comprising a PMU interface configured to couple the PMU to the processing unit and the MMP via a common bus and to a memory controller of the memory.

14. The apparatus of claim 13 , wherein the PMU interface is configured to couple the PMU to the memory controller via at least one of the memory bus or a direct connection.

15. The apparatus of claim 1 , wherein the adaptive memory controller configured to manage the memory based on the monitored statistical data comprises the adaptive memory controller configured to manage information depth and location based on traffic between the processing unit and the memory 220 .

16. The apparatus of claim 1 , wherein the adaptive memory controller configured to manage the memory based on the monitored statistical data comprises the adaptive memory controller configured to perform dynamic reconfiguration of the memory to match an information mapping with changing memory patterns of threads running on the processing unit.

17. A method, comprising:
retrieving, using a memory controller of a memory, information in at one of a non-volatile or volatile memory of the memory responsive to memory access requests received at the memory controller from a processing unit running a memory management hypervisor (MMH) operating system; and
managing a configuration of the memory at a memory management processor (MMP) running memory management threads (MMT) of the MMH operating system based on monitored statistical data, including:
changing a multi-level cell mode of a portion of memory;
managing mingration of information in the memory including managing metadata of page tables and translation lookaside buffers; and
responsive to receiving a memory access request for information stored in a portion of the memory undergoing a migration;
generating a page fault in the MMH operating system while the requested information is unavailable; and
providing the information when the portion of the memory become available.

18. The method of claim 17 , further comprising receiving the monitored statistical data associated with the memory and the processing unit.

19. The method of claim 17 , wherein the monitored statistical data associated with the memory comprises at least one of depth map setting of information stored at the memory, information mapping of and between portions of the memory, frequency of accesses of portions of the memory, or any combination thereof.

20. The method of claim 17 , wherein the monitored statistical data associated with the processing unit comprises at least one of types of the memory access requests, frequency of the memory accesses, idle time of the processing unit, or any combination thereof.

21. The method of claim 17 , wherein managing migration of information in the memory comprises:
providing memory commands to the memory; and
moving blocks of information in the memory responsive to the memory commands.

22. The method of claim 17 , wherein managing metadata of page tables and translation lookaside buffers further comprises storing the metadata in shadow page tables and translation lookaside buffers that are not visible to a guest operating system.

23. The method of claim 17 , wherein managing the configuration of the memory at the MMP running the MMH hypervisor operating system based on monitored statistical data associated with the memory and the processing unit comprises moving a portion of the memory from a first information depth map to an intermediate information depth map, wherein the intermediate information depth map is invisible to a processing unit running a guest operating system.

24. The method of claim 17 , wherein responsive to receipt of a memory access request to the portion of memory mappe

Assignees

• Micron Technology Inc

Inventors

• Roberts David A
• Pawlowski J Thomas
• Walker Robert

Classifications

• G06F12/023 Primary

  Free address space management · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F13/1694

  Configuration of memory controller to different memory types · CPC title

• Y02D10/13

  Cross-Sectional Technologies · mapped topic

• Y02D10/14

  Cross-Sectional Technologies · mapped topic