Integrated circuit device having a bit line and a main insulating spacer with an extended portion

Patent metadata

Field	Value
Publication number	US-11908797-B2
Application number	US-202017129083-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Jun 16, 2020
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a bit line on a substrate, the bit line comprising a lower conductive layer and an upper conductive layer;
an insulating capping pattern on the bit line; and
a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer comprising an extended portion opposite the upper conductive layer, the extended portion protruding toward the upper conductive layer compared to a portion of the main insulating spacer opposite the lower conductive layer,
wherein the extended portion of the main insulating spacer fills an undercut space corresponding to a sidewall of the upper conductive layer and a bottom surface of the insulating capping pattern, and
wherein the extended portion of the main insulating spacer and the portion of the main insulating spacer opposite the lower conductive portion form a continuous portion of a common material.

2. The integrated circuit device of claim 1 , wherein the sidewall of the bit line is oblique with respect to a surface of the substrate.

3. The integrated circuit device of claim 1 , wherein a width of the upper conductive layer is less in a horizontal direction than that of each of the insulating capping pattern and the lower conductive layer.

4. The integrated circuit device of claim 1 , further comprising a contact plug spaced apart from the bit line in a horizontal direction and connected to an active region of the substrate, the main insulating spacer being interposed between the contact plug and the bit line,
wherein the main insulating spacer comprises:
a first portion facing the insulating capping pattern and having a first width in the horizontal direction,
a second portion facing the upper conductive layer and having a second width in the horizontal direction, the second width being greater than the first width, and
a third portion facing the lower conductive layer and having a third width in the horizontal direction, the third width being less than the second width.

5. The integrated circuit device of claim 1 , wherein the sidewall of the upper conductive layer comprises a slanted sidewall facing the extended portion of the main insulating spacer, and
wherein a width of a portion of the main insulating spacer facing the upper conductive layer in a horizontal direction gradually increases from a bottom surface of the upper conductive layer to a top surface of the upper conductive layer.

6. The integrated circuit device of claim 1 , wherein the sidewall of the upper conductive layer comprises a nonlinear sidewall that is concave toward the extended portion,
wherein the main insulating spacer comprises:
a first portion facing the insulating capping pattern and having a first width in a horizontal direction, and
a second portion facing the nonlinear sidewall of the upper conductive layer and having a second width in the horizontal direction, the second width being greater than the first width.

7. The integrated circuit device of claim 1 , wherein the sidewall of the upper conductive layer comprises a nonlinear sidewall that is concave toward the extended portion, and
wherein a width of a bottom surface of the upper conductive layer is greater than a width of a top surface of the upper conductive layer.

8. The integrated circuit device of claim 1 , further comprising an inner insulating spacer on the sidewall of the bit line and the sidewall of the insulating capping pattern, the inner insulating spacer comprising a portion interposed between the upper conductive layer and the extended portion,
wherein the inner insulating spacer nonlinearly extends in a vertical direction.

9. The integrated circuit device of claim 1 , further comprising:
an inner insulating spacer interposed between the upper conductive layer and the extended portion; and
an outer insulating spacer spaced apart from the inner insulating spacer, the main insulating spacer being interposed between the outer insulating spacer and the inner insulating spacer,
wherein the main insulating spacer comprises an air spacer, a width of which corresponds to a distance between the inner insulating spacer and the outer insulating spacer.

10. An integrated circuit device comprising:
a bit line comprising a lower conductive layer and an upper conductive layer on the lower conductive layer in a vertical direction, the lower conductive layer being on a substrate and the upper conductive layer having a width less than a width of the lower conductive layer in a horizontal direction;
an insulating capping pattern on the upper conductive layer in the vertical direction, the insulating capping pattern having a width greater than the width of the upper conductive layer in the horizontal direction; and
a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer comprising an extended portion that is convex toward the upper conductive layer,
wherein the width of the upper conductive layer in the horizontal direction varies along the vertical direction.

11. The integrated circuit device of claim 10 , wherein the extended portion of the main insulating spacer comprises a portion which overlaps the insulating capping pattern in the vertical direction.

12. The integrated circuit device of claim 10 , wherein the main insulating spacer comprises a first portion facing the insulating capping pattern in the horizontal direction, a second portion facing the upper conductive layer in the horizontal direction, and a third portion facing the lower conductive layer in the horizontal direction, and
wherein a width of the second portion is greater than a width of each of the first portion and the third portion.

13. The integrated circuit device of claim 10 , further comprising:
a contact plug spaced apart from the bit line in the horizontal direction and connected to an active region of the substrate, the main insulating spacer being interposed between the contact plug and the bit line;
an inner insulating spacer between the upper conductive layer and the extended portion and covering the sidewall of the bit line; and
an outer insulating spacer between the main insulating spacer and the contact plug and covering the sidewall of the bit line,
wherein the main insulating spacer comprises a first sidewall that faces the inner insulating spacer along the extended portion and is convex toward the upper conductive layer, and a second sidewall that faces the outer insulating spacer on an opposite side of the extended portion in the horizontal direction and is linear along the vertical direction.

14. An integrated circuit device comprising:
a substrate comprising a plurality of active regions apart from each other, the plurality of active regions comprising a first active region and a second active region adjacent to the first active region;
a bit line connected to the first active region and comprising a lower conductive layer and an upper conductive layer stacked on the substrate in a vertical direction;
an insulating capping pattern on the bit line;
a contact plug adjacent to the bit line in a horizontal direction, the contact plug being connected to the second active region; and
a spacer structure between the bit line and the contact plug,
wherein the spacer structure comprises a main insulating spacer comprising an extended portion opposite the upper conductive layer, the extended portion protruding toward the upper conductive layer compared to a portion of the main insulating spacer opposite the lower conductive layer,
wherein the extende

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Jiyoung
• Han Seunguk
• Kim Sunghwan
• Park Seoryong
• Lee Kiseok
• Choi Yoonyoung
• Han Taehee
• Hong Jiseok

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title