Semiconductor memory device with selectively located air gaps

Patent metadata

Field	Value
Publication number	US-9620451-B2
Application number	US-201615092076-A
Country	US
Kind code	B2
Filing date	Apr 6, 2016
Priority date	Mar 5, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an inter-layer dielectric layer including contact hole over a substrate;
a first conductive plug disposed in the contact hole;
a bit line structure including a bit line and formed over the first conductive plug;
a second conductive plug formed over a sidewall of the first conductive plug and further extending over a sidewall of the bit line structure;
an insulating plug provided between the first conductive plug and the second conductive plug;
an air gap disposed between the bit line structure and the second conductive plug;
a third conductive plug formed over the second conductive plug while capping a first portion of the air gap; and
a capping layer formed over the third conductive plug while capping a second portion of the air gap,
wherein the first conductive plug and the bit line have the same line width,
wherein the insulating plug is formed inside of the contact hole and between a sidewall of the contact hole and the first conductive plug.

2. The semiconductor device of claim 1 , further comprising:
a protective spacer formed between the first conductive plug and the insulating plug and extending over the sidewall of the bit line structure.

3. The semiconductor device of claim 2 , wherein the protective spacer includes silicon nitride; and
wherein the insulating plug includes silicon nitride.

4. The semiconductor device of claim 1 , further comprising:
a protective spacer formed between the first conductive plug and the insulating plug and extending over the sidewall of the bit line structure;
a first spacer formed over an upper portion of the insulating plug and extending over a sidewall of the protective spacer; and
a second spacer formed over a sidewall of the first spacer,
wherein the air gap is disposed between the first spacer and the second spacer, and
wherein the first spacer and the second spacer collectively enclose the air gap.

5. The semiconductor device of claim 4 , wherein the protective spacer, the first spacer, and the second spacer respectively include silicon nitride.

6. The semiconductor device of claim 1 , wherein the first conductive plug and the second conductive plug include polysilicon, and
wherein the third conductive plug includes metal material.

7. The semiconductor device of claim 1 , further comprising:
an plug isolation layer formed between the bit line structure and a neighboring bit line structure, and further isolating the second conductive plug from a neighboring second conductive plug.

8. The semiconductor device of claim 1 , further comprising:
a buried gate-type transistor, including a buried word line, that is buried in the substrate; and
a memory element coupled with the third conductive plug.

9. The semiconductor device of claim 1 , wherein the substrate includes a memory cell region and a peripheral circuit region, and
the first conductive plug, the bit line structure, the second conductive plug, and the third conductive plug are formed in the memory cell region.

10. The semiconductor device of claim 8 , further comprising:
a non-buried-gate-type transistor formed over the substrate of the peripheral circuit region.

11. The semiconductor device of claim 1 , wherein the insulating plug surrounds partially the first conductive plug.

12. The semiconductor device of claim 1 , further comprising:
a multi-layer spacer formed between the bit line structure and the second conductive plug,
wherein the air gap is formed within the multi-layer spacer.

Assignees

• Sk Hynix Inc

Inventors

• Hwang Chang-Youn
• Kang Sang-Kil
• Joe Ill-Hee
• Park Dae-Sik
• Park Hae-Jung
• Kwon Se-Han

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title