Semiconductor device with air gap and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10490446-B2
Application number	US-201715800749-A
Country	US
Kind code	B2
Filing date	Nov 1, 2017
Priority date	Jun 30, 2015
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a conductive structure over a substrate, the conductive structure including a first plug and a conductive line over the first plug;
forming a dielectric plug at both sidewalls of the first plug, the dielectric plug including a sacrificial liner, the sacrificial liner having a first thickness;
forming a spacer at both sidewalls of the conductive line, the spacer including a sacrificial spacer, the sacrificial spacer having a second thickness;
forming a first air gap at the both sidewalls of the conductive line by removing the sacrificial spacer; and
forming a second air gap at the both sidewalls of the first plug by removing a part of the sacrificial liner,
wherein the dielectric plug includes a liner in contact with both sidewalls of the first plug and a filler over the liner, and the sacrificial liner is positioned between the liner and the filler.

2. The method of claim 1 ,
wherein the second thickness of the sacrificial spacer is larger than the first thickness of the sacrificial liner.

3. The method of claim 1 ,
wherein the sacrificial spacer and the sacrificial liner are formed of the same material.

4. The method of claim 1 ,
wherein the sacrificial spacer and the sacrificial liner are formed of silicon oxide.

5. The method of claim 1 ,
wherein the spacer further includes a first spacer in contact with both sidewalls of the conductive structure,
wherein the sacrificial spacer is formed over the first spacer, and
wherein the first spacer and the sacrificial spacer are formed in parallel to both sidewalls of the conductive structure.

6. The method of claim 1 , wherein the first air gap is formed in a line shape and in parallel to the both sidewalls of the conductive line.

7. The method of claim 1 , further comprising:
forming a second plug before the forming of the first air gap,
wherein the second plug includes a lower part and an upper part,
wherein the lower part is adjacent to the first plug,
wherein the upper part is adjacent to the conductive line, and
wherein the spacer and the dielectric plug are between the upper part and the conductive line.

8. The method of claim 7 , wherein the forming of the second plug comprises:
forming a sacrificial layer over the spacer;
forming a pre-isolation part and a sacrificial layer pattern by selectively etching the sacrificial layer;
forming a plug isolation layer to fill the pre-isolation part;
forming a second opening by removing the sacrificial layer pattern;
exposing the substrate under the second opening;
forming a conductive layer to fill the second opening; and
forming the second plug by recessing the conductive layer.

9. The method of claim 8 , further comprising:
forming a memory element coupled to the second plug,
wherein the conductive line includes a bit line.

10. The method of claim 1 , wherein the forming of the conductive structure comprises:
forming an interlayer dielectric layer over the substrate;
etching the interlayer dielectric layer and forming a first opening to expose a part of the substrate;
recessing the substrate exposed by the first opening to a predetermined depth;
forming a pre-first plug to fill the first opening;
forming a conductive layer over the pre-first plug;
forming the conductive line by etching the conductive layer; and
forming the first plug and a gap at both sidewalls of the first plug by etching the pre-first plug,
wherein the first plug has the same line width as the conductive line,
wherein the first air gap is positioned in the gap.

11. The method of claim 10 , wherein the forming of the dielectric plug comprises:
forming a first spacer layer over to cover the both sidewalls of the conductive line and the both sidewalls of the first plug;
forming a first sacrificial spacer layer over the first spacer layer by etching the sacrificial liner formed over first spacer layer;
forming a pre-filler layer over the first sacrificial spacer layer so as to fill the gap;
etching the pre-filler layer such that a filler is left in the gap; and
etching the first sacrificial spacer layer such that the sacrificial liner is left in the gap.

12. The method of claim 11 , wherein the forming of the spacer comprises:
forming a second sacrificial spacer layer over the first spacer layer, the etched first sacrificial spacer layer and the filler;
forming the second opening by etching the second sacrificial spacer layer to form the sacrificial spacer at a sidewall of the first spacer layer;
forming a second spacer layer over the entire surface including the sacrificial spacer and the second opening;
etching the second spacer layer to form a second spacer at a sidewall of the sacrificial spacer; and
cutting the first spacer layer to form a first spacer at a sidewall of the bit line.

13. The method of claim 12 , wherein each of the first and second spacers includes silicon nitride.

14. The method of claim 12 , wherein the etching of the second sacrificial spacer layer comprises:
forming a third sacrificial spacer layer over the second sacrificial spacer layer;
forming a plug isolation layer to provide a second opening, wherein the second opening exposes the third sacrificial spacer layer;
trimming the third sacrificial spacer layer to expose the second sacrificial spacer layer; and
etching the second sacrificial spacer layer to form the sacrificial spacer.

15. The method of claim 14 , wherein the forming of the plug isolation layer comprises:
forming a sacrificial layer over the third sacrificial spacer layer;
forming a pre-isolation part and a sacrificial layer pattern by selectively etching the sacrificial layer;
forming the plug isolation layer to fill the pre-isolation part; and
forming the second opening by removing the sacrificial layer pattern.

16. The method of claim 15 , wherein the trimming of the third sacrificial spacer layer comprises:
forming a re-capping layer on the entire surface of the resultant structure including the second opening;
forming a first buffer layer over the re-capping layer;
etching the first buffer layer and the re-capping layer to expose the third sacrificial spacer layer; and
trimming the third sacrificial spacer layer to expose the second sacrificial spacer layer.

17. The method of claim 12 , wherein the etching of the second spacer layer comprises:
forming a second buffer layer over the second spacer layer;
etching the second buffer layer to expose the second spacer layer; and
etching the second spacer layer to form the second spacer.

18. A method for fabricating a semiconductor device, comprising:
forming a conductive structure over a substrate, the conductive structure including a first plug and a conductive line over the first plug;
forming a dielectric plug at both sidewalls of the first plug, the dielectric plug including a sacrificial liner, the sacrificial liner having a first thickness;
forming a spacer at both sidewalls of the conductive line, the spacer including a sacrificial spacer, the sacrificial spacer having a second thickness;
forming a first air gap at the both sidewalls of the conductive line by removing the sacrificial spacer; and
forming a second air gap at the both sidewalls of the first plug by removing a part of the sacrificial liner,
wherein the second thickness of the sacrificial spacer is larger than the first thickness of the sacrificial liner.

19. A method for fabricating a semiconductor device, compris

Assignees

• Sk Hynix Inc

Inventors

• Park Hae-Jung
• Cheong Jung-Taik
• Jung Tae-Woo
• Choi Yun-Je

Classifications

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/43

  Layouts of interconnections · CPC title