Method for fabricating air gap adjacent to two sides of bit line

Patent metadata

Field	Value
Publication number	US-10418367-B2
Application number	US-201816029638-A
Country	US
Kind code	B2
Filing date	Jul 8, 2018
Priority date	May 17, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a bit line structure on the cell region and a gate structure on the peripheral region; forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure; forming a conductive layer on the bit line structure; performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure; forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and performing a second photo-etching process to remove part of the first cap layer on the cell region.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
providing a substrate having a cell region and a peripheral region;
forming a bit line structure on the cell region and a gate structure on the peripheral region;
forming an interlayer dielectric (ILD) layer around the bit line structure and the gate structure;
forming a conductive layer on the cell region and the peripheral region;
performing a first photo-etching process to remove part of the conductive layer for forming storage contacts adjacent two sides of the bit line structure and contact plugs adjacent to two sides of the gate structure;
forming a first cap layer on the cell region and the peripheral region to cover the bit line structure and the gate structure; and
performing a second photo-etching process to remove part of the first cap layer on the cell region.

2. The method of claim 1 , wherein the bit line structure is disposed along a first direction on the cell region.

3. The method of claim 2 , further comprising performing the first photo-etching process to remove part of the conductive layer along the first direction for forming the storage contacts.

4. The method of claim 1 , further comprising performing the second photo-etching process to remove part of the first cap layer along a second direction.

5. The method of claim 4 , wherein the second direction is orthogonal to the first direction.

6. The method of claim 1 , further comprising removing part of the ILD layer adjacent to two sides of the bit line structure for forming air gaps after performing the second photo-etching process.

7. The method of claim 6 , wherein the first cap layer is on the bit line structure and the air gaps.

8. The method of claim 7 , wherein the first cap layer is U-shaped.

9. The method of claim 1 , further comprising forming a second cap layer on the cell region and the peripheral region.

10. The method of claim 9 , wherein the second cap layer and the first cap layer comprise a dielectric material.

11. The method of claim 9 , wherein the first cap layer and the second cap layer comprise different material.

12. The method of claim 9 , wherein the second cap layer comprises silicon carbon nitride (SiCN).

13. The method of claim 1 , wherein the first cap layer comprises silicon nitride.

14. The method of claim 1 , wherein the ILD layer comprises silicon oxide.

15. The method of claim 1 , wherein the storage contacts comprise tungsten.

16. A method for fabricating semiconductor device, comprising:
providing a substrate having a cell region and a peripheral region;
forming a bit line structure on the cell region;
forming air gaps adjacent to two sides of the bit line structure;
forming a first cap layer on the bit line structure and the air gaps, wherein the first cap layer is U-shaped; and
forming a second cap layer on the first cap layer, wherein the second cap layer and the first cap layer comprise a dielectric material.

17. The method of claim 16 , further comprising forming storage contacts adjacent to two sides of the bit line structure.

18. The method of claim 17 , wherein a top surface of the storage contacts is even with the top surfaces of the first cap layer and the second cap layer.

19. The method of claim 16 , wherein the first cap layer and the second cap layer comprise different material.

20. The method of claim 16 , further comprising:
forming a gate structure on the peripheral region;
forming an interlayer dielectric (ILD) layer on the gate structure; and
forming contact plugs adjacent to two sides of the gate structure and within the ILD layer.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Chang Yi-Ching
• Chang Feng-Yi
• Lee Fu-Che
• Chen Chieh-Te

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H01L21/7682

  Electricity · mapped topic

• H01L27/10888

  Electricity · mapped topic