Semiconductor packages with die including cavities

Patent metadata

Field	Value
Publication number	US-11908699-B2
Application number	US-202217660477-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	Sep 17, 2015
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side opposite the first side;
a cavity extending into the second side of the semiconductor die and only partially through the semiconductor die;
a backmetal coupled within the cavity and directly coupled to an entirety of the second side; and
an organic material coupled over the first side of the semiconductor die and over a plurality of sidewalls of the semiconductor die;
wherein a first portion of the first side directly opposite the cavity is coplanar with a second portion of the first side at an outer edge of the first side.

2. The semiconductor package of claim 1 , wherein the organic material further comprises a die support structure.

3. The semiconductor package of claim 1 , wherein multiple surfaces of the backmetal form multiple outer surfaces of the semiconductor package.

4. The semiconductor package of claim 2 , wherein the organic material comprises a temporary die support structure.

5. The semiconductor package of claim 1 , further comprising one or more electrical contacts exposed through one or more openings in the organic material.

6. The semiconductor package of claim 1 , wherein a thinned portion of the semiconductor die is less than 5 microns thick.

7. A semiconductor package comprising:
a semiconductor die comprising a first side and a second side opposite the first side;
a cavity extending into the second side of the semiconductor die and only partially through the semiconductor die;
a backmetal coupled within the cavity; and
an organic material coupled over the first side of the semiconductor die and over an entirety of each sidewall of a plurality of sidewalls of the semiconductor die;
wherein an outer perimeter of the backmetal is a same size and shape as an outermost perimeter of the semiconductor die; and
wherein an entirety of the first side lies in a same plane and extends to the outermost perimeter of the semiconductor die.

8. The semiconductor package of claim 7 , wherein the organic material is directly coupled to the backmetal.

9. The semiconductor package of claim 7 , wherein the organic material further comprises a die support structure.

10. The semiconductor package of claim 7 , wherein a largest planar surface of the second side of the semiconductor die is within the cavity.

11. The semiconductor package of claim 7 , wherein a thinned portion of the semiconductor die is less than five microns thick.

12. The semiconductor package of claim 7 , further comprising one or more electrical contacts exposed through one or more openings in the organic material.

13. The semiconductor package of claim 7 , further comprising a conductive material coupled within the cavity.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Seddon Michael J
• Carney Francis J
• Chew Chee Hiong
• Wang Soon Wei
• Kurose Eiji

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title

• H10W74/016

  using moulds · CPC title