Processor frequency improvement based on antenna optimization

Patent metadata

Field	Value
Publication number	US-11906570-B2
Application number	US-202318296519-A
Country	US
Kind code	B2
Filing date	Apr 6, 2023
Priority date	Sep 21, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

First claim

What is claimed is:

1. A system configured to fabricating an integrated circuit (IC) having an increased processor frequency, the system comprising:
a controller configured to perform receive design data of the IC, the design data identifying a targeted gate and an antenna signal path and a gate threshold voltage, wherein the controller is configured to perform a plasma induced damage (PID) design exploitation to increase an amount of PID applied to the targeted gate to provide a PID-altered gate,
wherein the PID-altered gate and the antenna signal path are formed on a wafer.

2. The system of claim 1 , wherein the plasma induced damage (PID) design exploitation includes optimizing a ratio between a metal area corresponding to the antenna signal path and a gate area corresponding to the gate, the optimized ratio increases a level of plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage when forming the gate and the antenna signal path.

3. The system of claim 2 , wherein the optimized ratio includes performing at least one of: varying the metal area of the antenna signal path, varying an aspect ratio of the antenna signal path, and varying the gate area of the gate.

4. The system of claim 3 , wherein forming one or both of the gate and the antenna signal path according to the optimized ratio includes performing a plasma process that produces the plasma induced damage.

5. The system of claim 4 , wherein performing the PID design exploitation further includes:
predetermining an initial manufactured gate threshold voltage of the gate;
determining different levels of altered gate threshold voltages that occur in response to adjusting one or more antenna ratios of the gate;
determining a target gate threshold voltage of the gate; and
performing one or more of varying the metal area of the antenna signal path, varying the aspect ratio of the antenna signal path, and varying the gate area of the gate to change the gate threshold voltage to the target gate threshold voltage.

6. The system of claim 5 , wherein the gate threshold voltage has a first value and the target gate threshold voltage has a second voltage that is less than the first value of the gate threshold voltage.

7. The system of claim 6 , wherein the antenna ratio of the gate is a ratio of the metal area with respect to a combination of the gate area and an RX diffusion of the gate area.

8. The system of claim 2 , wherein altering the gate threshold voltage includes one of increasing or decreasing the gate threshold voltage to increase a switching speed of the gate.

9. The system of claim 8 , wherein the plasma process includes a plasma etching process.

10. The system of claim 9 , wherein adjusting the plasma process includes one or more of increasing plasma etch flux levels, increasing plasma etch duration times, and varying thicknesses of oxide materials located in non-etching regions.

11. The system of claim 8 , wherein the plasma process includes a plasma deposition process.

12. The system of claim 11 , wherein adjusting the plasma process includes one or more of increasing plasma deposition quantity levels and increasing plasma deposition duration times.

13. The system of claim 1 , wherein the controller stores at least one timing threshold corresponding to one or both of the antenna signal path and gate, performs a timing validation run on the gate having the altered gate voltage threshold, and determines a timing violation of the gate having the altered gate voltage threshold based on the timing validation run.

14. The system of claim 13 , wherein the PID-altered gate is to remove the timing violation.

15. The system of claim 14 , wherein the controller determines the timing violation by comparing a timing result obtained from the timing validation run to the at least one timing threshold, and determining the timing violation in response to the at least one timing result exceeding the at least one timing threshold.

Assignees

• IBM

Inventors

• Gonzalez Christopher
• Wolpert David
• Wood Michael Hemsley

Classifications

• G01R31/2623 Primary

  for measuring break-down voltage therefor · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F2117/12

  Sizing, e.g. of transistors or gates · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title