Semiconductor devices and methods for testing a gate insulation of a transistor structure

Patent metadata

Field	Value
Publication number	US-10079187-B2
Application number	US-201715497002-A
Country	US
Kind code	B2
Filing date	Apr 25, 2017
Priority date	Apr 28, 2016
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first test structure, wherein
the first test structure comprises a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device,
the first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer,
the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor,
the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure, and
a sum of a lateral area occupied by the first portion of the conductive structure of the first test structure and a lateral area occupied by the second portion of the conductive structure of the first test structure is at least larger than 10 times a lateral area occupied by the gate of the test transistor structure or the electrode of the test capacitor; and

a reference test structure comprising a first portion of a conductive structure and a second portion of the conductive structure located within the first lateral wiring layer, wherein
the first portion of the conductive structure of the reference test structure is electrically connected to the second portion of the conductive structure of the reference test structure through a third portion located within the second lateral wiring layer or a third lateral wiring layer of the layer stack arranged above the first lateral wiring layer,
the first portion of the conductive structure of the reference test structure is electrically connected to a gate of a reference transistor structure, a doping region of the reference transistor structure or an electrode of a reference capacitor, wherein the first portion of the conductive structure of the reference test structure is electrically connected to a first test pad of the reference test structure,
a sum of a lateral area occupied by the first portion of the conductive structure of the reference test structure and a lateral area occupied by the second portion of the conductive structure of the reference test structure is at least larger than 10 times a lateral area occupied by the gate of the test transistor structure or the electrode of the test capacitor,

a lateral area occupied by an antenna effect test portion of the conductive structure of the first test structure is at least 10% larger than a lateral area occupied by an antenna effect test portion of the conductive structure of the reference test structure, and
the antenna effect test portion of the conductive structure of the first test structure and the antenna effect test portion of the conductive structure of the reference test structure are located within the same wiring layer.

2. The semiconductor device according to claim 1 , wherein the antenna effect test portion of the conductive structure of the first test structure and the antenna effect test portion of the conductive structure of the reference test structure are located within a wiring layer above the first lateral wiring layer.

3. The semiconductor device according to claim 2 , wherein a lateral area occupied by the first portion of the conductive structure of the first test structure differs by less than 20% from a lateral area occupied by the first portion of the conductive structure of the reference test structure.

4. The semiconductor device according to claim 1 , wherein:
the antenna effect test portion of the conductive structure of the first test structure is represented by the first portion of the conductive structure of the first test structure; and
the antenna effect test portion of the conductive structure of the reference test structure is represented by the first portion of the conductive structure of the first test structure.

5. A semiconductor device comprising a plurality of test structures, wherein:
the plurality of test structures includes a first test structure;
the first test structure comprises a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device;
the first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer;
the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor;
the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure;
a sum of a lateral area occupied by the first portion of the conductive structure of the first test structure and a lateral area occupied by the second portion of the conductive structure of the first test structure is at least larger than 10 times a lateral area occupied by the gate of the test transistor structure or the electrode of the test capacitor;
each test structure of the plurality of test structures comprises an antenna effect test portion of the conductive structure of the respective test structure; and
the antenna effect test portions of the conductive structures of the test structures of the plurality of test structures occupy different lateral areas each.

6. The semiconductor device according to claim 5 , further comprising a reference test structure comprising a first portion of a conductive structure and a second portion of the conductive structure located within the first lateral wiring layer, wherein:
the first portion of the conductive structure of the reference test structure is electrically connected to the second portion of the conductive structure of the reference test structure through a third portion located within the second lateral wiring layer or a third lateral wiring layer of the layer stack arranged above the first lateral wiring layer;
the first portion of the conductive structure of the reference test structure is electrically connected to a gate of a reference transistor structure, a doping region of the reference transistor structure or an electrode of a reference capacitor, wherein the first portion of the conductive structure of the reference test structure is electrically connected to a first test pad of the reference test structure; and
a sum of a lateral area occupied by the first portion of the conductive structure of the reference test structure and a lateral area occupied by the second portion of the conductive structure of the reference test structure is at least larger than 10 times a lateral area occupied by the gate of the test transistor structure or the electrode of the test capacitor.

7. The semiconductor device according to claim 6 , wherein the first portion of the conductive structure of the reference test structure is electrically insulated from the second portion of the conductive structure of the reference test structure within the first lateral wiring layer.

8. The semiconductor device according to claim 6 , wherein the sum of the lateral area occupied by the first portion of the conductive structure of the first test str

Assignees

• Infineon Technologies Ag

Inventors

• Beckmeier Daniel
• Martin Andreas

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H01L22/14

  Electricity · mapped topic

• G01R31/2625

  for measuring gain factor thereof · CPC title