Method for generating aging model and manufacturing semiconductor chip using the same

Patent metadata

Field	Value
Publication number	US-10796050-B2
Application number	US-201916416762-A
Country	US
Kind code	B2
Filing date	May 20, 2019
Priority date	Nov 9, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A method for generating an aging model used in the design of a semiconductor chip includes: extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to a plurality of semiconductor elements included in the semiconductor chip from the plurality of aging scenarios; and generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter of each of the semiconductor elements.

First claim

What is claimed is:

1. A method for generating an aging model, used in design of a semiconductor chip that includes a plurality of semiconductor elements, the method comprising:
extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip;
calculating a first aging parameter commonly applied to each semiconductor element of the plurality of semiconductor elements from the plurality of aging scenarios, wherein the first aging parameter has a same value for each semiconductor element of the plurality of semiconductor elements; and
generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter, wherein a value of the second aging parameter corresponds to an individual semiconductor element of the plurality of semiconductor elements.

2. The method as claimed in claim 1 , wherein each of the plurality of aging scenarios includes bias information and usage time information of the semiconductor chip.

3. The method as claimed in claim 1 , wherein the first aging parameter includes stress time information affecting characteristic deterioration of the semiconductor chip.

4. The method as claimed in claim 1 , wherein calculating the first aging parameter includes:
acquiring at least one aging information from the plurality of aging scenarios; and
calculating the first aging parameter using the acquired aging information and a reference aging scenario stored in the aging model library.

5. The method as claimed in claim 1 , wherein the second aging parameter includes a probability in which each of the semiconductor elements is under stress conditions during use of the semiconductor chip.

6. The method as claimed in claim 1 , wherein the simulation is performed separately for each of the semiconductor elements under a preset reference operating voltage and reference operating temperature.

7. The method as claimed in claim 1 , wherein the characteristic deterioration information includes a threshold voltage variation of each of the semiconductor elements.

8. The method as claimed in claim 1 , further comprising: generating an aging model of each of the semiconductor elements, based on correlation among the first aging parameter and the second aging parameter, and the characteristic deterioration information.

9. The method as claimed in claim 8 , wherein the aging model is a machine learning model trained using the first aging parameter and the second aging parameter, and the characteristic deterioration information.

10. A method for generating an aging model, used in design of a semiconductor chip that includes a plurality of semiconductor elements, the method comprising:
calculating a first aging parameter of the semiconductor chip from a plurality of use conditions defined in an aging model library of the semiconductor chip;
generating characteristic deterioration information due to aging of each semiconductor element of the plurality of semiconductor elements included in the semiconductor chip using the first aging parameter and a second aging parameter; and
generating timing information due to aging of the semiconductor chip using the characteristic deterioration information and a third aging parameter of each semiconductor element of the plurality of semiconductor elements, wherein:
the first aging parameter has a same value for each semiconductor element of the plurality of semiconductor elements, and
a value of the second aging parameter corresponds to an individual semiconductor element of the plurality of semiconductor elements.

11. The method as claimed in claim 10 , wherein the first aging parameter is calculated by projecting merged aging information into a value under a preset reference use condition, after aging information of the semiconductor chip obtained from the plurality of use conditions is merged.

12. The method as claimed in claim 10 , wherein the first aging parameter includes stress time information affecting characteristic deterioration of the semiconductor chip.

13. The method as claimed in claim 10 , wherein the second aging parameter includes a probability in which each of the semiconductor elements is under stress conditions during use of the semiconductor chip.

14. The method as claimed in claim 10 , wherein the third aging parameter includes slew information, an output load value, and sensitivity information on timing delay change, of each of the semiconductor elements.

15. The method as claimed in claim 14 , wherein the sensitivity information is calculated in a liberty variation format (LVF) characterization process of the semiconductor chip.

16. The method as claimed in claim 10 , further comprising: generating an aging model of the semiconductor chip, based on correlation among the first to third aging parameters, and the timing information.

17. The method as claimed in claim 16 , wherein the aging model is a machine learning model trained using the first to third aging parameters and the timing information.

18. A method for manufacturing a semiconductor chip, the method comprising:
loading a plurality of aging scenarios from an aging model library of a semiconductor chip including a plurality of semiconductor elements;
acquiring a global aging parameter commonly applied to the semiconductor elements from the plurality of aging scenarios, wherein the global aging parameter has a same value for each semiconductor element of the plurality of semiconductor elements;
calculating one or more first timing delays of the semiconductor chip using the global aging parameter;
calculating a second timing delay of the semiconductor chip by summing the first timing delays;
determining whether the semiconductor chip violates timing constraints using the second timing delay; and
manufacturing the semiconductor chip when the semiconductor chip does not violate the timing constraint.

19. The method as claimed in claim 18 , wherein the global aging parameter includes stress time information affecting characteristic deterioration of the semiconductor chip.

20. The method as claimed in claim 18 , wherein the first timing delay is calculated using characteristic deterioration information and timing delay sensitivity information of each of the semiconductor elements.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Moon Su

Classifications

• G01R31/31704

  Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00) · CPC title

• G01R31/2848 Primary

  using simulation · CPC title

• G01R31/2872

  related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation · CPC title

• G01R31/2642

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• H10W74/01

  Manufacture or treatment · CPC title