Continuous gate and fin spacer for advanced integrated circuit structure fabrication
US-2024038578-A1 · Feb 1, 2024 · US
being in lateral device isolation regions, e.g. STI
being in lateral device isolation regions, e.g. STI · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10D30/795 |
| Official title | {being in lateral device isolation regions, e.g. STI} |
| Display label | being in lateral device isolation regions, e.g. STI |
| Total patents | 1,420 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 64 |
| 2016 | 64 |
| 2017 | 95 |
| 2018 | 145 |
| 2019 | 214 |
| 2020 | 236 |
| 2021 | 203 |
| 2022 | 115 |
| 2023 | 109 |
| 2024 | 87 |
| 2025 | 74 |
| 2026 | 14 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Segregated finfet structure and manufacturing method
US-2015364594-A1 · Dec 17, 2015 · US
Isolation structure of semiconductor device
US-9209066-B2 · Dec 8, 2015 · US
Shallow trench isolation
US-2015348830-A1 · Dec 3, 2015 · US
Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices
US-9202918-B2 · Dec 1, 2015 · US
Methods for producing integrated circuits with an insultating layer
US-2015340274-A1 · Nov 26, 2015 · US
Tunable Stressed Polycrystalline Silicon on Dielectrics in an Integrated Circuit
US-2015318394-A1 · Nov 5, 2015 · US
Methods for forming a semiconductor arrangement with structures having different heights
US-9178066-B2 · Nov 3, 2015 · US
Structure and Method for FinFET Device
US-2015311207-A1 · Oct 29, 2015 · US
Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices
US-2015294912-A1 · Oct 15, 2015 · US
Stress enhanced high voltage device
US-2015287780-A1 · Oct 8, 2015 · US
Shallow trench isolation
US-9136330-B2 · Sep 15, 2015 · US
Component, for example nmos transistor, with active region with relaxed compression stresses, and fabrication method
US-2015255540-A1 · Sep 10, 2015 · US
Dual shallow trench isolation (sti) field effect transistor (fet) and methods of forming
US-2015255539-A1 · Sep 10, 2015 · US
Integrated circuit comprising components, for example nmos transistors, having active regions with relaxed compressive stresses
US-2015249132-A1 · Sep 3, 2015 · US
Tuck strategy in transistor manufacturing flow
US-9123808-B2 · Sep 1, 2015 · US
Method to form strained channel in thin box soi structures by elastic strain relaxation of the substrate
US-2015243784-A1 · Aug 27, 2015 · US
Dielectric isolated fin with improved fin profile
US-2015243755-A1 · Aug 27, 2015 · US
Structure to Enhance Gate Induced Strain Effect in Multigate Devices
US-2015236021-A1 · Aug 20, 2015 · US
Semiconductor Device
US-2015228786-A1 · Aug 13, 2015 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10D30/795?
- CPC H10D30/795 is the Cooperative Patent Classification code for “being in lateral device isolation regions, e.g. STI.”
- How many patents are filed under CPC H10D30/795 (being in lateral device isolation regions, e.g. STI)?
- Our database includes 1,420 publications tagged with this CPC code.
- Is patent activity under CPC H10D30/795 growing?
- Publication counts under this code: 87 in 2024 vs 74 in 2025 (latest complete years).