Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11901453-B2
Application number	US-202217587402-A
Country	US
Kind code	B2
Filing date	Jan 28, 2022
Priority date	Jan 8, 2019
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a gate structure intersecting the active region and extending in a second direction on the substrate;
a source/drain region in a recess region of the active region in which the active region is recessed at a side of the gate structure; and
a plurality of channel layers on the active region, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the first direction and the second direction,
wherein the source/drain region includes:
a first epitaxial layer including first impurities of a first conductivity type; and
a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including second impurities of the first conductivity type,

wherein the first epitaxial layer has a first thickness on a side wall of the recess region and has a second thickness, greater than the first thickness, on a bottom surface of the recess region, and
wherein the gate structure surrounds the plurality of channel layers.

2. The semiconductor device as claimed in claim 1 , wherein the first epitaxial layer covers a lower surface and side surfaces of the second epitaxial layer.

3. The semiconductor device as claimed in claim 1 , wherein:
the first epitaxial layer includes the first impurities in a first concentration, and
the second epitaxial layer includes the second impurities in a second concentration that is higher than the first concentration.

4. The semiconductor device as claimed in claim 1 , wherein:
the first impurities include arsenic (As), and
the second impurities include phosphorus (P).

5. The semiconductor device as claimed in claim 1 , wherein:
the first epitaxial layer is a SiAs layer, and
the second epitaxial layer is a SiP layer.

6. The semiconductor device as claimed in claim 1 , wherein:
the first epitaxial layer further includes the second impurities, and
the second epitaxial layer further includes the first impurities.

7. The semiconductor device as claimed in claim 6 , wherein a concentration of the first impurities in the first epitaxial layer, in the second epitaxial layer, and in the active region has a maximum value in the first epitaxial layer.

8. The semiconductor device as claimed in claim 1 , wherein the first epitaxial layer extends along side surfaces of the plurality of channel layers in the third direction.

9. The semiconductor device as claimed in claim 1 , further comprising a contact plug connected to the source/drain region,
wherein a lower surface of the contact plug is on a level lower than a lower surface of an uppermost channel layer among the plurality of channel layers.

10. The semiconductor device as claimed in claim 1 , wherein an upper surface of the source/drain region is on a level higher than a level of a lower surface of the gate structure.

11. A semiconductor device, comprising:
an active region extending in a first direction on a substrate;
a plurality of channel layers on the active region, the plurality of channel layers being spaced apart from each other in a third direction perpendicular to the first direction;
a gate structure on the substrate intersecting the active region and the plurality of channel layers and extending in a second direction, the gate structure surrounding the plurality of channel layers; and
a source/drain region in a recess region of the active region in which the active region is recessed at a side of the gate structure, the source/drain region being in contact with the plurality of channel layers,
wherein the source/drain region includes:
a first epitaxial layer on side surfaces of the plurality of channel layers in the first direction, the first epitaxial layer including first impurities of a first conductivity type; and
a second epitaxial layer filling the recess region on the first epitaxial layer and including second impurities of the first conductivity type,

wherein the first epitaxial layer has a first thickness on a side wall of the recess region and has a second thickness, greater than the first thickness, on a bottom surface of the recess region.

12. The semiconductor device as claimed in claim 11 , wherein a thickness of the first epitaxial layer is not uniform and the first epitaxial layer has curvatures.

13. The semiconductor device as claimed in claim 11 , wherein the second thickness is at least twice as great as the first thickness.

14. The semiconductor device as claimed in claim 11 , wherein the first epitaxial layer covers a lower surface and side surfaces of the second epitaxial layer.

15. The semiconductor device as claimed in claim 11 , wherein the second epitaxial layer is spaced apart from the active region.

16. The semiconductor device as claimed in claim 11 , further comprising internal spacer layers on both sides of the gate structure on a lower surface of each of the plurality of channel layers,
wherein the first epitaxial layer protrudes more in the first direction towards the second epitaxial layer on side surfaces of the internal spacer layers than on the side surfaces of the plurality of channel layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Sung Uk
• Kim Ki Hwan
• Jung Su Jin
• Kim Bong Soo
• Cho Young Dae

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title