Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9941405-B2
Application number	US-201615340951-A
Country	US
Kind code	B2
Filing date	Nov 1, 2016
Priority date	Mar 21, 2016
Publication date	Apr 10, 2018
Grant date	Apr 10, 2018

Abstract

A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.

First claim

What is claimed is:

1. A method of manufacturing a nanosheet or nanowire device from a stack comprising an alternating arrangement of sacrificial layers and channel layers on a substrate, the method comprising:
deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode; and
forming conductive passivation layers in the electrode recesses, each conductive passivation layer extending at least partially along a side of one of the electrode recesses, wherein portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers; and
epitaxially growing the source and drain electrodes in the electrode recesses, wherein the source and drain electrodes are grown from the substrate and wherein the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.

2. The method of claim 1 , further comprising performing an anisotropic etch to remove portions of the passivation layers covering the substrate at the lower ends of the electrode recesses.

3. The method of claim 1 , wherein the conductive passivation layers extend completely along sides of the electrode recesses.

4. The method of claim 1 , wherein the conductive passivation layers extend only partially along sides of the electrode recesses.

5. The method of claim 1 , further comprising laterally recessing the channel layers before the forming of the conductive passivation layers.

6. The method of claim 1 , further comprising annealing or crystallizing the conductive passivation layers.

7. The method of claim 1 , further comprising:
performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers; and
forming internal spacers in the internal spacer recesses.

8. The method of claim 1 , wherein each conductive passivation layer comprises a conductive oxide.

9. The method of claim 8 , wherein the conductive oxide is RuO 2 or oxygen deficient TiO 2 .

10. The method of claim 1 , wherein each conductive passivation layer has a thickness from approximately 0.2 nm to approximately 2 nm.

11. The method of claim 1 , wherein each conductive passivation layer has a thickness from approximately 0.2 nm to approximately 1 nm.

12. The method of claim 1 , wherein each conductive passivation layer has a thickness from approximately 0.2 nm to approximately 0.5 nm.

13. The method of claim 1 , wherein the epitaxially growing the source and drain electrodes in the electrode recesses comprises repeatedly forming portions grown from the channel layers and portions grown from the substrate and anisotropically etching to selectively remove the portions grown from the channel layers.

14. The method of claim 1 , further comprising:
etching remaining portions of the sacrificial layers to form cavities; and
depositing gate stacks in the cavities.

15. A method of manufacturing a nanosheet or nanowire device from a stack comprising an alternating arrangement of sacrificial layers and channel layers on a substrate, the method comprising:
deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode; and
forming conductive passivation layers in the electrode recesses, each conductive passivation layer extending at least partially along a side of one of the electrode recesses, wherein portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers; and
epitaxially growing the source and drain electrodes in the electrode recesses,
wherein the source and drain electrodes are grown from the substrate and wherein the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers, and
wherein the epitaxially growing the source and drain electrodes in the electrode recesses comprises repeatedly growing portions of the source and drain electrodes and anisotropically etching to selectively remove any portions grown from the channel layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kittl Jorge A
• Wang Wei-E
• Rodder Mark S

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H01L29/165

  Electricity · mapped topic

• H01L21/30604

  Electricity · mapped topic