Sacrificial fin for self-aligned contact rail formation

Patent metadata

Field	Value
Publication number	US-11901440-B2
Application number	US-202117465316-A
Country	US
Kind code	B2
Filing date	Sep 2, 2021
Priority date	Sep 2, 2021
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.

First claim

What is claimed is:

1. A semiconductor device comprising:
a functional gate structure including a first source/drain region located a first end of a semiconductor channel material structure and a second source/drain region located at a second end of the semiconductor channel material structure; and
a contact rail located laterally adjacent to the functional gate structure and contacting a surface of the first source/drain region of the functional gate structure, wherein the contact rail has a lower portion having a first critical dimension and an upper portion having a second critical dimension that is greater than the first critical dimension, wherein the first critical dimension is 25 nm or less.

2. The semiconductor device of claim 1 , wherein the semiconductor channel material structure is an active semiconductor fin and the functional gate structure is located laterally adjacent a sidewall of the active semiconductor fin.

3. The semiconductor device of claim 2 , wherein the first source/drain region is a bottom source/drain structure, and the second source/drain region is a top source/drain region.

4. The semiconductor device of claim 1 , further comprising a source/drain contact structure contacting the second source/drain region, and a gate contact structure contacting a gate conductor material of the functional gate structure.

5. The semiconductor device of claim 4 , wherein the contact rail has a topmost surface that is coplanar with a topmost surface of each of the source/drain contact structure and the gate contact structure.

6. The semiconductor device of claim 1 , wherein the contact rail is a discrete contact rail.

7. The semiconductor device of claim 1 , wherein the contact rail is a via bar contact rail.

8. The semiconductor device of claim 1 , wherein the contact rail is embedded in at least an interlayer dielectric material layer.

9. The semiconductor device of claim 8 , wherein the contact rail is further embedded in a middle-of-the-line (MOL) level dielectric stack that is present atop the interlayer dielectric material layer.

10. A semiconductor device comprising:
a functional gate structure including a first source/drain region located a first end of a semiconductor channel material structure and a second source/drain region located at a second end of the semiconductor channel material structure; and
a contact rail located laterally adjacent to the functional gate structure and contacting a surface of the first source/drain region of the functional gate structure, wherein an entirety of the contact rail has a constant critical dimension in a direction along the semiconductor channel material structure.

11. The semiconductor device of claim 10 , wherein the first source/drain region is a bottom source/drain structure, and the second source/drain region is a top source/drain region.

12. The semiconductor device of claim 11 , further comprising a source/drain contact structure contacting the second source/drain region, and a gate contact structure contacting a gate conductor material of the functional gate structure.

13. The semiconductor device of claim 12 , wherein the contact rail has a topmost surface that is coplanar with a topmost surface of each of the source/drain contact structure and the gate contact structure.

14. The semiconductor device of claim 12 , wherein the contact rail is a via bar contact rail.

15. The semiconductor device of claim 11 , wherein the contact rail is embedded in at least an interlayer dielectric material layer.

16. The semiconductor device of claim 15 , wherein the contact rail is further embedded in a middle-of-the-line (MOL) level dielectric stack that is present atop the interlayer dielectric material layer.

17. A method of forming a semiconductor device, the method comprising:
forming at least one sacrificial semiconductor fin in a first region of a semiconductor substrate and at least one active semiconductor fin in a second region of the semiconductor substrate, wherein the at least one sacrificial semiconductor fin has a first critical dimension;
forming a source/drain region on the semiconductor substrate in the first region including the at least one sacrificial semiconductor fin and the second region including the at least one active semiconductor fin;
forming a functional gate structure in the second region and laterally adjacent to the at least one active semiconductor fin;
forming a dielectric material stack adjacent to, and above, the at least one sacrificial semiconductor fin and the at least one active semiconductor fin;
forming an opening in the dielectric material stack that physically exposes the at least one sacrificial semiconductor fin, wherein the opening has a second critical dimension that is greater than the first critical dimension of the at least one sacrificial semiconductor fin;
removing the at least one sacrificial semiconductor fin to provide a contact rail opening having a lower portion having the first critical dimension and an upper portion having the second critical dimension, the contact rail opening physically exposes a surface of the source/drain region; and
forming a contact rail in the contact rail opening and on the physically exposed surface of the source/drain region.

18. The method of claim 17 , wherein the dielectric material stack includes at least a middle-of-the-line (MOL) level dielectric stack.

19. The method of claim 17 , wherein the opening is a discrete opening.

20. The method of claim 17 , opening is a via bar opening.

Assignees

• IBM

Inventors

• Mignot Yann
• Waskiewicz Christopher J
• Fan Su Chen
• Anderson Brent
• Wang Junli

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title