Self-aligned single dummy fin cut with tight pitch

Patent metadata

Field	Value
Publication number	US-10242881-B2
Application number	US-201715813518-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	Aug 9, 2016
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.

First claim

What is claimed is:

1. An apparatus comprising:
a first set of spacers comprising a first material formed on a substrate; and
a second set of spacers comprising a second material formed on the substrate, the second set of spacers adjacent to the first set of spacers on the substrate, the second material comprising metal oxide;
wherein an etch process applied to the first set of spacers removes the first set of spacers at a first etch rate;
wherein the etch process applied to the second set of spacers removes the second of spacers at a second etch rate;
wherein the first etch rate is different than the second etch rate:
a mask material layer formed on the first set and on the second set of spacers;
an opening in the mask material layer, the opening having first and second sidewalk, wherein none of the mask material layer is in the opening formed by the first and second sidewalls, wherein a bottom of the opening is not formed of the mask material layer;
a bottom surface of the first sidewall positioned on a top surface of a first spacer of the second set of spacers, the first spacer of the second set of spacers adjacent to a first spacer if the first set of spacers; and
a bottom surface of the second sidewall positioned on a top surface of a second spacer of the second set of spacers, the second spacer of the second set of spacers opposite to the first spacer of the second set of spacers and adjacent to the first spacer of the first set of spacers.

2. The apparatus of claim 1 , wherein the spacing between each adjacent spacer is less than about 40 nm.

3. The apparatus of claim 1 , wherein the first material comprises an oxide.

4. The apparatus of claim 3 , wherein the oxide is silicon dioxide.

5. The apparatus of claim 1 , wherein the metal oxide comprises aluminum oxide.

6. The apparatus of claim 1 , wherein the first and second etch rates are with respect to a same etchant.

7. The apparatus of claim 6 , wherein the first etch rate is greater than the second etch rate and the second etch rate is zero or effectively zero.

8. The apparatus of claim 1 , wherein the metal oxide is formed by sequential infiltration synthesis (SIS) of a polymer.

9. The apparatus of claim 8 , wherein the polymer is formed by directed self-assembly (DSA) of a block copolymer.

10. The apparatus of claim 1 , wherein the bottom surface of the first sidewall stops on the top surface of the first spacer of the second set of spacers;
wherein the bottom surface of the second sidewall stops on the top surface of the second spacer of the second set of spacers.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Chi Cheng
• Liu Chi-Chun
• Xu Peng

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/694 Primary

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H01L21/0337

  Electricity · mapped topic

• H01L21/31116

  Electricity · mapped topic