Semiconductor device

Patent metadata

Field	Value
Publication number	US-11901433-B2
Application number	US-202117410648-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	Aug 29, 2015
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

First claim

What is claimed is:

1. A device, comprising:
a first III-V compound layer;
a second III-V compound layer over the first III-V compound layer;
a dielectric layer over the second III-V compound layer;
a source/drain contact extending through the dielectric layer to the second III-V compound layer, wherein the source/drain contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer;
a metal-containing layer over and in contact with the source/drain contact and a portion of the metal-containing layer is directly above the dielectric layer; and
a metal contact over and in contact with the metal-containing layer, wherein a bottommost surface of the metal-containing layer is wider than a bottommost surface of the metal contact and a pate field plate between a pate structure and the source/drain contact.

2. The device of claim 1 , wherein a bottom portion of the source/drain contact is embedded in the second III-V compound layer.

3. The device of claim 1 , further comprising an etch stop layer over the metal-containing layer.

4. The device of claim 3 , wherein the etch stop layer laterally surrounds a bottom of the metal contact.

5. The device of claim 3 , wherein a sidewall of the etch stop layer is substantially aligned with a sidewall of the metal-containing layer.

6. The device of claim 1 , further comprising a gate structure over the second III-V compound layer.

7. The device of claim 1 , wherein the gate field plate is made of a material the same as a material of the metal-containing layer.

8. A device, comprising:
a first III-V compound layer;
a second III-V compound layer over the first III-V compound layer;
a source/drain contact over the second III-V compound layer, wherein a bottom portion of the source/drain contact is embedded in the second III-V compound layer, and an ohmic connection is formed between the source/drain contact and the second III-V compound layer;
a dielectric layer over the second III-V compound layer and laterally surrounding the source/drain contact;
a metal contact over the source/drain contact; and
an etch stop layer over the source/drain contact and laterally surrounding the metal contact.

9. The device of claim 8 , further comprising an anti-reflective coating (ARC) layer between the source/drain contact and the etch stop layer.

10. The device of claim 9 , wherein a sidewall of the ARC layer is substantially aligned with a sidewall of the etch stop layer.

11. The device of claim 8 , further comprising a gate structure over the second III-V compound layer.

12. The device of claim 11 , further comprising an ARC layer over the gate structure.

13. The device of claim 12 , wherein the ARC layer is free from coverage by the etch stop layer.

14. A device, comprising:
a first III-V compound layer;
a second III-V compound layer over the first III-V compound layer;
a source contact and a drain contact over the second III-V compound layer, wherein an ohmic connection is formed between the source contact and the second III-V compound layer;
a first metal-containing layer and a second metal-containing layer respectively over the source contact and the drain contact;
a gate field plate over the second III-V compound layer and between the source contact and the drain contact, wherein the gate field plate is made of a material a same as a material of the first metal-containing layer; and a first oxide layer and a second oxide layer respectively over the first metal-containing layer and the second metal-containing layer, wherein a sidewall of the first oxide layer is substantially aligned with a sidewall of the first metal-containing layer.

15. The device of claim 14 , wherein the gate field plate is at a position lower than the first metal-containing layer.

16. The device of claim 14 , wherein the gate field plate is free from coverage by the first oxide layer.

17. The device of claim 14 , further comprising a gate structure between the source contact and the gate field plate.

18. The device of claim 1 , wherein the first III-V compound layer is a gallium nitride (GaN) layer, and the second III-V compound layer is an aluminum gallium nitride (AlGaN) layer.

19. The device of claim 14 , wherein the first III-V compound layer is a gallium nitride (GaN) layer.

20. The device of claim 14 , wherein the second III-V compound layer is an aluminum gallium nitride (AlGaN) layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• You Jheng-Sheng
• Lin Hsin-Chih
• Huang Kun-Ming
• Chen Lieh-Chuan
• Chu Po-Tao
• Wang Shen-Ping
• Kuo Chien-Li

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title