High electron mobility transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9231093-B2
Application number	US-201313804188-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Jul 20, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A high electron mobility transistor (HEMT) according to example embodiments includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a Schottky electrode forming a Schottky contact with the channel supply layer. An upper surface of the channel supply layer may define a Schottky electrode accommodation unit. At least part of the Schottky electrode may be in the Schottky electrode accommodation unit. The Schottky electrode is electrically connected to the source electrode.

First claim

What is claimed is:

1. A high electron mobility transistor (HEMT) comprising:
a channel layer;
a channel supply layer on the channel layer,
an upper surface of the channel supply layer defining a Schottky electrode accommodation unit;
a source electrode and a drain electrode on at least one of the channel layer and the channel supply layer;
a gate electrode between the source electrode and the drain electrode such that the Schottky electrode accommodation unit of the channel supply layer is between the gate electrode and the drain electrode; and
at least part of a Schottky electrode in the Schottky electrode accommodation unit of the channel supply layer,
the Schottky electrode forming a Schottky contact with the channel supply layer, and
the Schottky electrode is electrically connected to the source electrode,
the Schottky electrode accommodation unit is a recess defined by the upper surface of the channel supply layer and separated from an interface between the channel layer and the channel supply layer,
a distance from a bottom portion of the Schottky electrode accommodation unit to the interface between the channel layer and the channel supply layer is maintained at a level at which a concentration of a two-dimensional electron gas (2DEG) formed in the channel layer below the Schottky electrode is equal or greater than about 90% of a concentration of the 2DEG formed in an adjacent region of the channel layer and less than about 100% of the concentration of the 2DEG formed in the adjacent region of the channel layer when a voltage is not applied to the Schottky electrode,

the distance from the bottom portion of the Schottky electrode accommodation unit to the interface between the channel layer and the channel supply layer is in a range from a first thickness of the channel supply layer to a second thickness of the channel supply layer,
the first thickness of the channel supply layer corresponds to the level at which the concentration of the 2DEG formed in the channel layer below the Schottky electrode is equal to about 90% of the concentration of the 2DEG formed in the adjacent region of the channel layer, and
the second thickness of the channel supply layer is greater than the first thickness of the channel supply layer and less than a thickness of an other portion of the channel supply layer that is above the adjacent region of the channel layer, and a ratio of the second thickness to the first thickness is about 4.

2. The HEMT of claim 1 , wherein the distance from the bottom portion of the Schottky electrode accommodation unit to the interface between the channel layer and the channel supply layer is about 6 nm or greater.

3. The HEMT of claim 1 , wherein the Schottky electrode accommodation unit is discontinuously formed along a width direction of the channel layer.

4. The HEMT of claim 3 , wherein
a plurality of the Schottky electrode accommodation units are arranged along the width direction of the channel layer, and
the plurality of the Schottky electrode accommodation units are spaced apart from each other.

5. The HEMT of claim 1 , wherein the Schottky electrode accommodation unit is continuously formed along a width direction of the channel layer.

6. The HEMT of claim 1 , wherein the Schottky electrode includes:
a first electrode layer on the channel supply layer; and
a second electrode layer contacting the first electrode layer,
wherein a work function of the second electrode is greater than a work function of the first electrode layer.

7. The HEMT of claim 6 , wherein at least a part of the second electrode layer is in the Schottky electrode accommodation unit.

8. The HEMT of claim 1 , wherein the upper surface of the channel supply layer further defines a gate electrode accommodation unit between the source electrode and the Schottky electrode.

9. The HEMT of claim 8 , wherein
the gate electrode accommodation unit is a recess defined by the upper surface of the channel supply layer.

10. The HEMT of claim 9 , wherein
the gate electrode accommodation unit exposes the interface between the channel layer and the channel supply layer, or
the gate electrode accommodation unit exposes a portion of the channel layer that is lower than the interface between the channel layer and the channel supply layer.

11. The HEMT of claim 8 , further comprising:
an insulating layer between the gate electrode accommodation unit and the gate electrode.

12. The HEMT of claim 1 , further comprising:
a depletion forming layer between the gate electrode and the channel layer.

13. The HEMT of claim 12 , wherein the depletion forming layer is a p-type semiconductor layer.

14. The HEMT of claim 1 , further comprising:
a first pad contacting the source electrode and the Schottky electrode; and
a second pad contacting the drain electrode.

15. The HEMT of claim 14 , wherein the first pad further includes a field plate over the Schottky electrode.

16. The HEMT of claim 14 , further comprising:
a passivation layer between the gate electrode and the first pad.

17. The HEMT of claim 1 , wherein
the channel supply layer includes a first thickness between a lowermost surface of the Schottky electrode and an uppermost surface of the channel layer,
the channel supply layer includes a second thickness between an uppermost surface of the channel supply layer and a bottommost surface of the channel supply layer,
the second thickness is greater than the first thickness,
a bottommost surface of the gate electrode is separated from the uppermost surface of the channel layer by a first distance, and
a value of the first distance is different than a value of the first thickness.

18. The HEMT of claim 6 , wherein
a bottommost surface of the first electrode layer is directly on an uppermost surface of the channel supply layer, and
a bottommost surface of the second electrode layer is on an upper surface of the channel supply layer at the bottom of the Schottky electrode accommodation unit.

19. The HEMT of claim 1 , further comprising at least one of wherein
a first pad contacting the source electrode and the Schottky electrode; and
a second pad contacting the drain electrode, wherein
the first thickness of the channel supply layer is 6 nm and the second thickness of the channel supply layer is 25 nm.

20. A high electron mobility transistor (HEMT) comprising:
a channel layer;
a channel supply layer on the channel layer,
an upper surface of the channel supply layer defining a Schottky electrode accommodation unit;
a source electrode and a drain electrode on at least one of the channel layer and the channel supply layer;
a gate electrode between the source electrode and the drain electrode such that the Schottky electrode accommodation unit of the channel supply layer is between the gate electrode and the drain electrode; and
at least part of a Schottky electrode in the Schottky electrode accommodation unit of the channel supply layer,
the Schottky electrode forming a Schottky contact with the channel supply layer, and

the Schottky electrode is electrically connected to the source electrode,
the Schottky electrode accommodation unit is a recess defined by the upper surface of the channel supply layer and separated from an interface between the channel layer and the channel supply layer,
a distance from a bottom portion of the Schottky electrode accommodation unit to the interface between the channel layer and the channel supply layer is maintained in a range from 6 nm to 25 nm s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Woo-Chul
• Kim Kyoung-Yeon
• Kim Jong-Seob
• Kim Joon-Yong
• Park Ki-Yeol
• Park Young-Hwan
• Shin Jai-Kwang
• Oh Jae-Joon
• Choi Hyuk-Soon
• Ha Jong-Bong
• Hwang Sun-Kyu
• Hwang In-Jun

Classifications

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/111

  Field plates · CPC title

• H10D64/64

  Electrodes comprising a Schottky barrier to a semiconductor · CPC title