Interconnect architecture with silicon interposer and EMIB

Patent metadata

Field	Value
Publication number	US-11901299-B2
Application number	US-202218079753-A
Country	US
Kind code	B2
Filing date	Dec 12, 2022
Priority date	Dec 28, 2018
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

First claim

What is claimed is:

1. An electronic package, comprising:
a package substrate;
an interposer on the package substrate;
a first die stack and a second die stack on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die stack to the second die stack;
a die on the package substrate; and
an interconnect bridge on the package substrate, wherein the interconnect bridge electrically couples the interposer to the die.

2. The electronic package of claim 1 , wherein the first die stack and the second die stack comprise field-programmable gate array (FPGA) dies.

3. The electronic package of claim 1 , wherein the first die stack and the second die stack each comprise an IC base die and a plurality of memory dies stacked over the IC base die.

4. The electronic package of claim 3 , wherein the plurality of memory dies have a footprint that is larger than a footprint of the IC base die.

5. The electronic package of claim 1 , further comprising:
first interconnects coupling the first die stack and the second die stack to the interposer, wherein the first interconnects have a first pitch;
second interconnects coupling the interposer to the interconnect bridge and the die to the interconnect bridge, wherein the second interconnects have a second pitch that is larger than the first pitch; and
third interconnects coupling the interposer to the package substrate, wherein the third interconnects have a third pitch that is larger than the first pitch, wherein the first, second, and third interconnects comprise solder interconnects or copper-to-copper interconnects.

6. The electronic package of claim 1 , wherein the interposer comprises silicon.

7. The electronic package of claim 1 , wherein the interposer is a passive interposer.

8. The electronic package of claim 1 , wherein the interposer is an active interposer.

9. The electronic package of claim 1 , wherein the interconnect bridge comprises silicon, ceramic, or organic materials.

10. The electronic package of claim 1 , wherein the die is a transceiver, a high bandwidth memory (HBM), or any other stack of memory architectures.

11. An electronic package, comprising:
a package substrate;
a first interconnect bridge on the package substrate;
a first interposer over the package substrate;
a first plurality of die stacks on the first interposer; and
a first die on the package substrate, wherein the first die is electrically coupled to the first interposer by the first interconnect bridge.

12. The electronic package of claim 11 , wherein the first plurality of die stacks comprises a 2×2 array of die stacks.

13. The electronic package of claim 11 , wherein the first plurality of die stacks comprises an M×N array of die stacks, wherein M is 1 or more, and wherein N is 1 or more.

14. The electronic package of claim 13 , wherein the first plurality of die stacks are electrically coupled to each other by conductive traces in the interposer.

15. The electronic package of claim 11 , further comprising:
a second interposer over the package substrate, wherein the second interposer is electrically coupled to the first interposer by a second interconnect bridge on the package substrate.

16. The electronic package of claim 15 , further comprising:
a second plurality of die stacks on the second interposer.

17. The electronic package of claim 16 , wherein at least one of the second plurality of die stacks is over the second interposer and the first interposer.

18. The electronic package of claim 11 , further comprising:
a second die on the package substrate, wherein the second die is electrically coupled to the first interposer by a second interconnect bridge.

19. The electronic package of claim 11 , wherein the first die is a high bandwidth memory, an in-package memory die, or a transceiver.

20. The electronic package of claim 11 , wherein the die stacks in the first plurality of die stacks each comprise an IC base die and a plurality of stacked memory dies over the IC base die.

21. The electronic package of claim 20 , wherein a footprint of the stacked memory dies is larger than a footprint of the IC base die.

22. The electronic package of claim 11 , wherein the interposer is a passive silicon interposer.

23. An electronic package comprising:
a package substrate, the package substrate having a plurality of interconnect bridges thereon;
a first interposer over the package substrate, the first interposer comprising silicon;
a first plurality of die stacks on the first interposer, wherein each of the first plurality of die stacks comprises a field-programmable gate array (FPGA), and wherein the first plurality of die stacks are electrically coupled together by conductive traces in the first interposer, and wherein first interconnects electrically couple the first plurality of die stacks to the first interposer, wherein the first interconnects have a first pitch; and
a first die on the package substrate, wherein the first die is electrically coupled to the first interposer by the one of the interconnect bridges in the plurality of interconnect bridges, wherein second interconnects electrically couple the first interposer to the one of the interconnect bridges and the first die to the one of the interconnect bridges, wherein the second interconnects have a second pitch that is larger than the first pitch.

24. The electronic package of claim 23 , wherein the FPGA comprises an advanced process node relative to the first die.

25. The electronic package of claim 23 , further comprising a plurality of memory dies stacked over each FPGA.

Assignees

• Intel Corp

Inventors

• Hossain Md Altaf
• Nalamalpu Ankireddy
• Subbareddy Dheeraj
• Sankman Robert
• Mahajan Ravindranath V
• Mallik Debendra
• Viswanath Ram S
• Sane Sandeep B
• Srinivasan Sriram
• Agarwal Rajat
• Dasu Aravind
• Weber Scott
• Gutala Ravi

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title