Integrated circuits and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11894463-B2
Application number	US-202318093877-A
Country	US
Kind code	B2
Filing date	Jan 6, 2023
Priority date	Jun 17, 2019
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit, the method comprising:
alternately forming a plurality of semiconductor layers and a plurality of sacrificial layers on a substrate;
patterning the plurality of semiconductor layers and the plurality of sacrificial layers to form a channel stack extending in a first direction;
forming a dummy gate structure on the channel stack, the dummy gate structure including a dummy gate insulating layer pattern and a dummy gate;
forming a spacer structure on a sidewall of the dummy gate structure, the spacer structure including a first spacer layer and a second spacer layer, the first spacer layer including a portion overhanging laterally and outwardly;
forming a plurality of semiconductor patterns and forming a recess region by removing a portion of the channel stack, the portion of the channel stack being not covered by the spacer structure, and an uppermost one of the plurality of semiconductor patterns having an inverted trapezoidal cross-section and an inclined sidewall;
forming a semiconductor layer in the recess region;
forming a gate space by removing the dummy gate structure and the plurality of sacrificial layers, the gate space including sub gate spaces between the plurality of semiconductor patterns; and
forming a gate electrode in the gate space.

2. The method as claimed in claim 1 , wherein forming the semiconductor layer includes forming the semiconductor layer in the recess region such that a portion of a top surface of the semiconductor layer is in contact with a bottom surface of the spacer structure.

3. The method as claimed in claim 1 , wherein, during forming of the semiconductor layer, the inclined sidewall of the uppermost one of the plurality of semiconductor patterns is in contact with the semiconductor layer.

4. The method as claimed in claim 1 , wherein the uppermost one of the plurality of semiconductor patterns includes a tail portion under the spacer structure.

5. The method as claimed in claim 1 , wherein, during forming of the gate space, a center portion of a top surface of the uppermost one of the plurality of semiconductor patterns is exposed, not being covered by the spacer structure, while an edge portion of an upper surface of the uppermost one of the plurality of semiconductor patterns is covered by the spacer structure.

6. The method as claimed in claim 1 , wherein a top surface of the uppermost one of the plurality of semiconductor patterns has a first width in the first direction, and a bottom surface of the uppermost one of the plurality of semiconductor patterns has a second width smaller than the first width in the first direction.

7. The method as claimed in claim 6 , wherein the gate electrode includes:
a main gate part disposed on the uppermost one of the plurality of semiconductor patterns; and
a plurality of sub gate parts disposed between two corresponding patterns among the plurality of semiconductor patterns,
wherein a bottom surface of the main gate part has a third width in the first direction, and an intermediate portion of the main gate part has a fourth width different from the third width in the first direction.

8. The method as claimed in claim 7 , wherein the third width is smaller than the first width.

9. The method as claimed in claim 7 , wherein:
the main gate part includes a bottom portion having a sloped sidewall,
the sloped sidewall of the main gate part is vertically overlapped with at least a portion of the spacer structure, and
at least a portion of a bottom surface of the spacer structure is under the sloped sidewall of the main gate part.

10. A method of manufacturing an integrated circuit, the method comprising:
alternately forming a plurality of semiconductor layers and a plurality of sacrificial layers on a substrate;
patterning the plurality of semiconductor layers and the plurality of sacrificial layers to form a channel stack extending in a first direction;
forming a dummy gate structure on the channel stack, the dummy gate structure including a dummy gate insulating layer pattern and a dummy gate;
forming a spacer structure on a sidewall of the dummy gate structure, the spacer structure including a first spacer layer and a second spacer layer, the first spacer layer including a portion overhanging laterally and outwardly;
forming a plurality of semiconductor patterns and forming a recess region by removing a portion of the channel stack, the portion of the channel stack being not covered by the spacer structure, and an uppermost one of the plurality of semiconductor patterns including an inclined sidewall;
forming a semiconductor layer in the recess region, a portion of the semiconductor layer contacting the inclined sidewall, and the portion of the semiconductor layer vertically overlapping the spacer structure;
forming a gate space by removing the dummy gate structure and the plurality of sacrificial layers; and
forming a gate electrode in the gate space,
wherein a top surface of the uppermost one of the plurality of semiconductor patterns has a first width in the first direction, and a bottom surface of the uppermost one of the plurality of semiconductor patterns has a second width smaller than the first width in the first direction.

11. The method as claimed in claim 10 , wherein, during forming of the gate space, a center portion of a top surface of the uppermost one of the plurality of semiconductor patterns is exposed, not being covered by the spacer structure, while an edge portion of an upper surface of the uppermost one of the plurality of semiconductor patterns is covered by the spacer structure.

12. The method as claimed in claim 10 , wherein the gate electrode includes:
a main gate part disposed on the uppermost one of the plurality of semiconductor patterns; and
a plurality of sub gate parts disposed between two corresponding patterns among the plurality of semiconductor patterns,
wherein a bottom surface of the main gate part has a third width in the first direction, and an intermediate portion of the main gate part has a fourth width different from the third width in the first direction.

13. The method as claimed in claim 12 , wherein the third width is smaller than the first width.

14. The method as claimed in claim 12 , wherein:
the main gate part includes a bottom portion having a sloped sidewall,
the spacer structure includes a sidewall portion in contact with the sloped sidewall of the main gate part, and
at least a portion of a bottom surface of the spacer structure is under the sloped sidewall of the main gate part.

15. The method as claimed in claim 14 , wherein forming the dummy gate structure includes:
forming a dummy gate insulating layer on an upper surface of the channel stack;
forming a dummy gate layer on the dummy gate insulating layer;
patterning the dummy gate insulating layer and the dummy gate layer to form the dummy gate insulating layer pattern and the dummy gate, such that a portion of the dummy gate insulating layer pattern protrudes outwardly with respect to a sidewall of the dummy gate; and
removing the portion of the dummy gate insulating layer pattern, such that the dummy gate insulating layer pattern is recessed inwardly with respect to the sidewall of the dummy gate.

16. The method as claimed in claim 15 , wherein:
during forming of the spacer structure, the sidewall portion of the spacer structure is in contact with the dummy gate insulating layer, and
during forming of the gate electrode, the sloped sidewall of the main gate part is in contact with the sidewall portio

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Seungmin
• Suh Bongseok
• Yang Junggil
• Jeong Soojin

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/794

  comprising conductive materials, e.g. silicided source, drain or gate electrodes · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title