Semiconductor device

Patent metadata

Field	Value
Publication number	US-10217816-B2
Application number	US-201615296077-A
Country	US
Kind code	B2
Filing date	Oct 18, 2016
Priority date	Mar 2, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of channels sequentially stacked on a substrate, the plurality of channels spaced apart from each other in a first direction perpendicular to a top surface of the substrate;
source/drain layers at opposite sides of the plurality of channels in a second direction parallel to the top surface of the substrate, the source/drain layers connected to the plurality of channels; and
a gate structure enclosing the plurality of channels, wherein the plurality of channels have different lengths in the second direction and different thicknesses in the first direction, wherein each of the source/drain layers includes:
an epitaxial layer on the substrate; and
extension portions extending from the epitaxial layer in the second direction and respectively connected to the plurality of channels.

2. The semiconductor device as claimed in claim 1 , wherein the thicknesses of the plurality of channels in the first direction are in a proportional relationship to the lengths of the plurality of channels in the second direction.

3. The semiconductor device as claimed in claim 2 , wherein:
the lengths of the plurality of channels in the second direction increase in a predetermined direction, and
the thicknesses of the plurality of channels in the first direction increase in the predetermined direction.

4. The semiconductor device as claimed in claim 2 , wherein:
a length of each of an uppermost channel and a lowermost channel of the plurality of channels in the second direction is greater than a length of an intermediate channel of the plurality of channels in the second direction, and
a thickness of each of the uppermost channel and the lowermost channel of the plurality of channels in the first direction is greater than a thickness of the intermediate channel of the plurality of channels in the first direction.

5. The semiconductor device as claimed in claim 1 , wherein the extension portions include:
substantially a same material as the plurality of channels, and
a same impurity as the epitaxial layer.

6. The semiconductor device as claimed in claim 1 , wherein the epitaxial layer and the extension portions include different materials and a same impurity.

7. The semiconductor device as claimed in claim 1 , wherein:
the epitaxial layer has a substantially vertical sidewall along the first direction, and
the extension portions have lengths in the second direction that progressively decrease in a downward direction.

8. The semiconductor device as claimed in claim 1 , wherein:
the epitaxial layer has a width in the second direction that progressively decreases in a predetermined direction, and
the extension portions have a constant length in the second direction in the predetermined direction.

9. The semiconductor device as claimed in claim 1 , wherein:
the epitaxial layer has a greater width in the second direction at a middle portion than at an upper portion or at a lower portion, and
extension portions have a substantially constant length in the second direction.

10. The semiconductor device as claimed in claim 1 , further comprising: an inner spacer between the gate structure and the epitaxial layer.

11. The semiconductor device as claimed in claim 10 , wherein the gate structure includes:
a gate insulating pattern enclosing each of the plurality of channels; and
a gate electrode at least partially covered by the gate insulating patterns, the gate electrode extending in a third direction parallel to the top surface of the substrate and perpendicular to the second direction.

12. A semiconductor device, comprising:
a pair of first semiconductor patterns on a substrate, the pair of first semiconductor patterns spaced apart from each other in a first direction parallel to a top surface of the substrate;
second semiconductor patterns between the pair of first semiconductor patterns and connected to the pair of first semiconductor patterns, the second semiconductor patterns spaced apart from each other in a second direction perpendicular to the top surface of the substrate; and
a gate structure between the pair of first semiconductor patterns and covering the second semiconductor patterns, wherein each of the second semiconductor patterns includes a central portion between end portions in the first direction, the end portions of the second semiconductor patterns including a same impurity as the pair of first semiconductor patterns, and the central portions of the second semiconductor patterns having different lengths and different thicknesses from each other, a change in the different lengths of the central portions being directly proportional to a change in the different thicknesses of the central portions.

13. The semiconductor device as claimed in claim 12 , wherein the thicknesses and the lengths of the central portions of the second semiconductor patterns increase in a predetermined direction.

14. The semiconductor device as claimed in claim 12 , wherein:
the pair of first semiconductor patterns have substantially vertical sidewalls in the second direction, and
the lengths of the end portions of the second semiconductor patterns decrease in a predetermined direction.

15. The semiconductor device as claimed in claim 12 , wherein:
the pair of first semiconductor patterns have a width decreasing in a predetermined direction, and
the lengths of the end portions of the second semiconductor patterns are substantially constant in the predetermined direction.

16. The semiconductor device as claimed in claim 15 , wherein the gate structure includes a gate insulating pattern partially enclosing the second semiconductor patterns, and a gate electrode at least partially covered by the gate insulating patterns.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bhuwalka Krishna Kumar
• Kim Seong-Je
• Kim Jong-Chol
• Kim Hyun-Woo

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/1037

  Electricity · mapped topic

• H01L29/0665 Primary

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L29/775

  Electricity · mapped topic