Distributed semiconductor die and package architecture

Patent metadata

Field	Value
Publication number	US-11894359-B2
Application number	US-202217574485-A
Country	US
Kind code	B2
Filing date	Jan 12, 2022
Priority date	Jan 12, 2018
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

First claim

What is claimed:

1. A method, comprising:
forming a first plurality of conductors on an upper surface of a base die;
forming a second plurality of conductors on the upper surface of the base die, wherein:
each of the first plurality of conductors is disposed on the upper surface of the base die and is spaced apart from the remaining first plurality of conductors;
each of the second plurality of conductors is disposed on the upper surface of the base die and is spaced apart from the remaining second plurality of conductors; and
each of the first plurality of conductors intersects and conductively couples to at least one of the second plurality of conductors on the upper surface of the base die, the first plurality of conductors and the second plurality of conductors conductively coupled to circuitry included in the base die; and

conductively coupling each of a plurality of cores to a node formed by an intersection of one of the first plurality of conductors with one of the second plurality of conductors, wherein each of the plurality of cores comprises processor core circuitry.

2. The method of claim 1 , wherein forming a second plurality of conductors on the upper surface of the base die further comprises:
forming the second plurality of conductors on the upper surface of the base die such that each of the second plurality of conductors are disposed orthogonally to at least one of the first plurality of conductors.

3. The method of claim 1 , wherein forming a second plurality of conductors on the upper surface of the base die further comprises:
forming the second plurality of conductors on the upper surface of the base die such that each of the second plurality of conductors are disposed orthogonally to each of the first plurality of conductors.

4. The method of claim 1 , wherein forming a second plurality of conductors on the upper surface of the base die further comprises:
forming the second plurality of conductors on the upper surface of the base die such that each of the second plurality of conductors intersects and conductively couples to each of the first plurality of conductors.

5. The method of claim 1 , further comprising:
forming, in the base die, a plurality of through-silicon-vias (TSV)s that conductively couple at least one of: the first plurality of conductors and the second plurality of conductors or the I/O circuitry to contact pads disposed on the lower surface of the base die.

6. The method of claim 1 , further comprising:
forming at least one active element proximate the upper surface of the base die.

7. The method of claim 6 , wherein forming at least one active element proximate the upper surface of the base die further comprises:
forming at least one transistor proximate the upper surface of the base die.

8. The method of claim 7 , further comprising:
conductively coupling the at least one transistor to the first plurality of conductors and
the second plurality of conductors.

9. The method of claim 1 , further comprising:
forming at least one transistor proximate a lower surface of at least some of the plurality of cores; and
conductively coupling each of the at least one transistors proximate the lower surface of at least some of the plurality of cores to the first plurality of conductors and the second plurality of conductors.

10. The method of claim 1 :
wherein forming a first plurality of conductors on an upper surface of a base die further comprises: patterning each of the first plurality of conductors on the upper surface of the base die;
wherein forming a second plurality of conductors on an upper surface of a base die further comprises patterning each of the second plurality of conductors on the upper surface of the base die.

11. The method of claim 1 , further comprising:
forming at least one of: input/output (I/O) circuitry, voltage regulator circuitry, controller circuitry, and memory circuitry in the base die.

12. The method of claim 1 , further comprising:
forming input/output circuitry in the base die; and
conductively coupling, via the first plurality of conductors and the second plurality of conductors, the I/O circuitry in the base die to the processor core circuitry included in at least one of the plurality of cores.

13. An apparatus, comprising:
a first plurality of conductors on an upper surface of a base semiconductor die;
a second plurality of conductors on the upper surface of the base semiconductor die, wherein:
each of the first plurality of conductors is disposed on the upper surface of the base semiconductor die and is spaced apart from the remaining first plurality of conductors;
each of the second plurality of conductors is disposed on the upper surface of the base semiconductor die and is spaced apart from the remaining second plurality of conductors; and
each of the first plurality of conductors intersects and conductively couples to at least one of the second plurality of conductors on the upper surface of the base semiconductor die, the first plurality of conductors and the second plurality of conductors conductively coupled to circuitry included in the base semiconductor die; and

each of a plurality of cores conductively coupled to a node formed by an intersection of one of the first plurality of conductors with one of the second plurality of conductors, wherein each of the plurality of cores comprises processor core circuitry.

14. The apparatus of claim 13 , wherein the second plurality of conductors is on the upper surface of the base semiconductor die such that each of the second plurality of conductors are disposed orthogonally to at least one of the first plurality of conductors.

15. The apparatus of claim 13 , wherein the second plurality of conductors is on the upper surface of the base semiconductor die such that each of the second plurality of conductors are disposed orthogonally to each of the first plurality of conductors.

16. The apparatus of claim 13 , wherein the second plurality of conductors is on the upper surface of the base semiconductor die such that each of the second plurality of conductors intersects and conductively couples to each of the first plurality of conductors.

17. The apparatus of claim 13 , further comprising:
a plurality of through-silicon-vias (TSV)s in the base semiconductor die, wherein the plurality of TSVs conductively couple at least one of: the first plurality of conductors and the second plurality of conductors or the I/O circuitry to contact pads disposed on the lower surface of the base semiconductor die.

18. The apparatus of claim 13 , further comprising:
at least one active element proximate the upper surface of the base semiconductor die.

19. The apparatus of claim 18 , further comprising:
at least one transistor proximate the upper surface of the base semiconductor die.

20. The apparatus of claim 19 , wherein the at least one transistor is conductively coupled to the first plurality of conductors and the second plurality of conductors.

21. The apparatus of claim 13 , further comprising:
at least one transistor proximate a lower surface of at least some of the plurality of cores; and
each of the at least one transistors proximate the lower surface of at least some of the plurality of cores conductively coupled to the first plurality of conductors and the second plurality of conductors.

22. The apparatus of claim 13 , further comprising:
at least one of: input/output (I/O) circuitry, voltage regulator circuitry, control

Assignees

• Intel Corp

Inventors

• Gomes Wilfred
• Bohr Mark T
• Kumar Rajesh
• Sankman Robert L
• Mahajan Ravindranath V
• Mccullough Wesley D

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title