Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Die-stacked device with partitioned multi-hop network
US9065722B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9065722-B2 |
| Application number | US-201213726142-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2012 |
| Priority date | Dec 23, 2012 |
| Publication date | Jun 23, 2015 |
| Grant date | Jun 23, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.
First claim
Opening claim text (preview).
What is claimed is: 1. An electronic assembly comprising: an interposer; a plurality of die disposed at a surface of the interposer and connected via one or more metal layers of the interposer; and a multi-hop network to route packets among the plurality of die, the multi-hop network comprising a router partition and a link partition, the routing partition comprising routing logic disposed at each die of at least a subset of the plurality of die and the link partition comprisi…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9065722B2 cover?
- An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link…
- Who is the assignee on this patent?
- Advanced Micro Devices Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 23 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).