Three-dimensional memory device containing amorphous and crystalline blocking dielectric layers

Patent metadata

Field	Value
Publication number	US-11894298-B2
Application number	US-202217655827-A
Country	US
Kind code	B2
Filing date	Mar 22, 2022
Priority date	Nov 26, 2019
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming memory openings vertically extending through the alternating stack;
forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel that extend vertically, and each memory film comprises a blocking dielectric metal oxide layer and a continuous silicon oxide liner that laterally surrounds the blocking dielectric metal oxide layer;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory opening fill structures;
dividing each continuous silicon oxide liner into a respective vertical stack of silicon oxide liners by performing an etch process to physically expose segments of outer sidewalls of the respective blocking dielectric metal oxide layer;
forming a dielectric metal oxide layer directly on physically exposed surfaces of the insulating layers and directly on the physically exposed segments of the outer sidewalls of the blocking dielectric metal oxide layers; and
forming electrically conductive layers in remaining volumes of the backside recesses directly on the dielectric metal oxide layer.

2. The method of claim 1 , wherein the blocking dielectric metal oxide layers are formed as amorphous dielectric metal oxide layers, and are subsequently converted into crystalline blocking dielectric metal oxide layers by an anneal process.

3. The method of claim 2 , wherein the dielectric metal oxide layer is depo sited directly on the crystalline blocking dielectric metal oxide layers.

4. The method of claim 2 , further comprising: forming drain regions in the memory opening fill structures at an upper end of a respective one of the semiconductor channels; and forming source regions in, or on, upper portions of the substrate.

5. The method of claim 1 , further comprising forming a blocking dielectric semiconductor compound layer on a respective one of the blocking dielectric metal oxide layers within each of the memory openings.

6. The method of claim 5 , further comprising forming a charge storage layer and a tunneling dielectric layer on a respective one of the blocking dielectric semiconductor compound layers within each of the memory openings, wherein each of the memory films comprises a respective continuous silicon oxide liner, a respective blocking dielectric metal oxide layer, a respective blocking dielectric semiconductor compound layer, a respective charge storage layer, and a respective tunneling dielectric layer, and wherein each of the semiconductor channels is formed on a respective one of the tunneling dielectric layers.

7. The method of claim 1 , wherein: each of the blocking dielectric metal oxide layers consists essentially of a first aluminum oxide material; and the dielectric metal oxide layer consists essentially of a second aluminum oxide material.

8. The method of claim 7 , wherein: the first aluminum oxide material is deposited in an amorphous phase and is subsequently converted into a polycrystalline aluminum oxide material prior to formation of the dielectric metal oxide layer; and the dielectric metal oxide layer is deposited in an amorphous phase and remains amorphous until after formation of the electrically conductive layers.

9. The method of claim 1 , further comprising: forming backside trenches through the alternating stack after formation of the memory opening fill structures; isotropically etching the sacrificial material layers selective to the insulating layers and the memory opening fill structures by introducing an isotropic etchant into the backside trenches; and conformally depositing the dielectric metal oxide layer on physically exposed surfaces of the backside trenches and the backside recesses.

10. The method of claim 9 , further comprising: forming a metallic liner on the dielectric metal oxide layer; and filling remaining volumes of the backside recesses with a conductive fill material.

11. The method of claim 1 , further comprising: forming stepped surfaces in a staircase region by patterning the alternating stack; forming a retro-stepped dielectric material portion of the stepped surfaces of the alternating stack; and forming contact via structures on a respective one of the electrically conducive layers through the retro-stepped dielectric material portion.

12. A semiconductor structure comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings vertically extending through the alternating stack;
memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel that extend vertically, and each memory film comprises a blocking dielectric metal oxide layer and a vertical stack of silicon oxide liners that are vertically spaced apart, contact a respective one of the insulating layers, and laterally surround the blocking dielectric metal oxide layer; and
dielectric metal oxide layers located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the blocking dielectric metal oxide layers and each of the electrically conductive layers, wherein each of the electrically conductive layers is in direct contact with a respective one of the dielectric metal oxide layers.

13. The semiconductor structure of claim 12 , wherein each of the electrically conductive layers comprises a respective metallic nitride liner that contacts the dielectric metal oxide layer and respective tungsten conductive fill material portion that is embedded in the respective metallic nitride liner.

14. The semiconductor structure of claim 12 , wherein the dielectric metal oxide layer contacts a sidewall of the blocking dielectric metal oxide layer in the memory opening fill structure.

15. The semiconductor structure of claim 12 , further comprising drain regions located in the memory opening fill structures and contacting an upper end of a respective one of the semiconductor channels.

16. The semiconductor structure of claim 12 , wherein:
each of the memory opening fill structures further comprises a silicon oxide blocking dielectric, a charge storage layer and a tunneling dielectric layer; and
each of the semiconductor channels is located on a respective one of the tunneling dielectric layers in each memory opening fill structure.

17. The semiconductor structure of claim 12 , wherein: each of the blocking dielectric metal oxide layers consists essentially of a polycrystalline a luminum oxide material; and the dielectric metal oxide layer consists essentially of an amorphous aluminum oxide material.

18. The semiconductor structure of claim 12 , further comprising:
retro-stepped dielectric material portions overlying stepped surfaces of the alternating stack;
a pair of insulating spacers laterally spaced apart from each other, vertically extending from a bottommost layer of the alternating stack to a topmost layer of the alternating stack, and contacting each layer within the alternating stack; and
a pair of backside contact via structures laterally surrounded by a respective one of the pair of insulating spacers,

wherein:
each of the electrically conductive layers consists of a respective crystalline metallic liner and a respective meta

Assignees

• Sandisk Technologies Llc

Inventors

• Tsutsumi Masanori
• Hosoda Naohiro
• Hamaguchi Shuichi
• Isozumi Kazuki
• Mizuno Genta
• Mukae Yusuke
• Nakamura Ryo
• Ueda Yu

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H01L23/5226 Primary

  Electricity · mapped topic

• H01L23/53223

  Electricity · mapped topic