Transistors with metal chalcogenide channel materials

Patent metadata

Field	Value
Publication number	US-11888034-B2
Application number	US-201916435358-A
Country	US
Kind code	B2
Filing date	Jun 7, 2019
Priority date	Jun 7, 2019
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZS x or IGZSe x ) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

First claim

What is claimed is:

1. A transistor structure, comprising:
a first semiconductor material of a first composition comprising one or more d-block or p-block metals;
a second semiconductor material of a first thickness and of a second composition, different than the first composition, in contact with the first semiconductor material, wherein at least the second semiconductor material comprises a chalcogen, and one or more d-block or p-block metals;
a source contact metal and a drain contact metal electrically coupled to both the first and second semiconductor materials therebetween, wherein each of the source contact metal and the drain contact metal extends through the first thickness of the second semiconductor material and is in contact with the first semiconductor material; and
a gate electrode material separated from the second semiconductor material by at least a gate dielectric material, the gate electrode material to control a channel region within at least one of the first or second semiconductor materials.

2. The transistor structure of claim 1 , wherein:
the first semiconductor material further comprises oxygen;
the first and second semiconductor materials both comprise the same one or more metals; and
the source contact metal is electrically coupled to the drain contact metal by a channel region within each of the first and second semiconductor materials.

3. The transistor structure of claim 1 , wherein
the first semiconductor material further comprises a chalcogen; and
the first and second semiconductor materials comprise different metals.

4. The transistor structure of claim 3 , wherein the first semiconductor material has a first conductivity type and the second semiconductor material has a second conductivity type, complementary to the first conductivity type.

5. The transistor structure of claim 1 , wherein the first and second semiconductor materials comprise at least one of Zn, Cd, Al, Sn, Ga, In, P, As, or Sb.

6. The transistor structure of claim 5 , wherein the chalcogen comprises S or Se, and wherein the first semiconductor material comprises MS x , MSe x , or MTe x , where M is the metal and x is between 0.2 and 4.

7. The transistor structure of claim 1 , wherein:
the first semiconductor material is over a substrate dielectric material;
the second semiconductor material is over the first semiconductor material;
the gate dielectric material is over the second semiconductor material; and
the gate electrode material is over the gate dielectric material.

8. The transistor structure of claim 7 , wherein:
a non-planar body comprises the substrate dielectric material; and
the first and second materials, the gate dielectric material, and the gate electrode material are adjacent to a sidewall of the non-planar body.

9. An integrated circuit (IC) die, comprising:
a plurality of complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) structures, wherein individual ones of the CMOS FET structures comprise a Group IV semiconductor material;
a plurality of back-end transistor structures over the CMOS FET structures, with one or more levels of interconnect metallization therebetween, wherein individual ones of the back-end transistor structures comprise the transistor structure of claim 1 .

10. The transistor structure of claim 1 , wherein the d-block or p-block metal comprises Zn.

11. The transistor structure of claim 10 , wherein the d-block or p-block metal comprises In y , Ga z , and Zn 1-y-z and wherein y and z are both greater than 0, but sum to less than 1.

12. The transistor structure of claim 1 , wherein the gate dielectric comprises predominantly oxygen and Ga or W.

13. The transistor structure of claim 1 , wherein:
the gate electrode material is a first gate electrode material within a stack of materials comprising the first and second semiconductor materials and further comprising a second gate electrode material;
the second semiconductor material is between the first semiconductor material and the first gate electrode material; and
the first semiconductor material is between the second semiconductor material and the second gate electrode material.

14. The transistor structure of claim 13 , wherein the gate dielectric material is a first gate dielectric material and the stack of materials further comprises a second gate dielectric material between the first semiconductor material and the second gate electrode material.

15. The transistor structure of claim 13 , wherein:
the first semiconductor material comprises oxygen; and
the first and second semiconductor materials both comprise the same one or more metals.

16. The transistors structure of claim 1 , wherein the second semiconductor material is in contact with the first semiconductor material over an entirety of the channel region.

17. The transistor structure of claim 1 , wherein the first semiconductor material has a second thickness and wherein each of the source contact metal and the drain contact metal extends through the second thickness of the first semiconductor material.

18. The transistor structure of claim 1 , wherein the gate electrode material is one of one or more gate electrode materials that are to control a channel region within each of the first and second semiconductor materials.

19. The transistor structure of claim 1 , wherein the channel region is within the second semiconductor material, and wherein the second semiconductor material has a thickness of less than 10 nm.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek A
• Agarwal Ashish
• Alaan Urusa
• Jezewski Christopher
• Lin Kevin
• Naylor Carl

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title