Structure for finFET CMOS

Patent metadata

Field	Value
Publication number	US-9576960-B2
Application number	US-201514693918-A
Country	US
Kind code	B2
Filing date	Apr 23, 2015
Priority date	Mar 21, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal.

First claim

What is claimed is:

1. A structure comprising:
an integrated circuit substrate;
an n-type fin set in an nFET region on the integrated circuit substrate;
a p-type fin set in a pFET region on the integrated circuit substrate;
a gate stack disposed over the n-type fin set and the p-type fin set;
a gate spacer disposed over the n-type fin set and the p-type fin set and on opposite sides of the gate stack;
a first doped epitaxial material on a source region and a drain region of the p-type fin set, wherein the source and drain regions of the p-type fin set is above the top surface of the integrated circuit substrate, and the gate spacer has a first spacer thickness between the first doped epitaxial material and the gate stack; and
a second doped epitaxial material on a source region and a drain region of the n-type fin set, wherein the source and drain region of the n-type fin set is above the top surface of the integrated circuit substrate, the first doped epitaxial material is different than the second doped epitaxial material, the gate spacer has a second spacer thickness between the second doped epitaxial material and the gate stack, and wherein the first spacer thickness is equal to the second spacer thickness.

2. The structure of claim 1 , wherein the first doped epitaxial material is a boron doped epitaxial material.

3. The structure of claim 1 , wherein the second doped epitaxial material is a phosphorus doped epitaxial material.

4. The structure of claim 1 , further comprising:
a carbon doped silicon (Si:C) layer formed on at least one fin of the n-type fin set and on at least one fin of the p-type fin set.

5. The structure of claim 4 , wherein the (Si:C) layer has a thickness between 1 nm and 5 nm.

6. The structure of claim 4 , wherein the carbon content of the (Si:C) layer is between 2% and 2.5%.

7. An integrated circuit structure comprising:
an n-type fin set in an nFET region on the integrated circuit substrate;
a p-type fin set in a pFET region on the integrated circuit substrate;
a gate stack disposed over the n-type fin set and the p-type fin set;
a gate spacer disposed over the n-type fin set and the p-type fin set and on opposite sides of the gate stack, wherein the gate spacer has a first thickness in the pFET region and a second thickness in the nFET region, and wherein the first thickness is equal to the second thickness;
a first doped epitaxial material on a source region and a drain region of the p-type fin set, wherein the source and drain regions of the p-type fin set is above the top surface of the integrated circuit substrate, and the gate spacer having the first thickness is between the first doped epitaxial material and the gate stack;
a second doped epitaxial material on a source region and a drain region of the n-type fin set, the source and drain region of the n-type fin set is above the top surface of the integrated circuit substrate, the first doped epitaxial material is different than the second doped epitaxial material, the second doped epitaxial material formed by the steps of:
forming a mask over the first doped epitaxial material and the gate spacer in the pFET region;
removing the first doped epitaxial material from the nFET region; and
forming the second doped epitaxial material on the source region and the drain region of the n-type fin set.

8. The structure of claim 7 , wherein the first doped epitaxial material is a boron doped epitaxial material.

9. The structure of claim 7 , wherein the second doped epitaxial material is a phosphorus doped epitaxial material.

10. The structure of claim 7 , further comprising:
a carbon doped silicon (Si:C) layer formed on at least one fin of the n-type fin set and on at least one fin of the p-type fin set.

11. The structure of claim 10 , wherein the (Si:C) layer has a thickness between 1 nm and 5 nm.

12. The structure of claim 10 , wherein the carbon content of the (Si:C) layer is between 2% and 2.5%.

Assignees

• IBM

Inventors

• Khakifirooz Ali
• Cheng Kangguo
• Reznicek Alexander

Classifications

• H01L27/1211

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic

• H01L29/167

  Electricity · mapped topic