RRAM structures in the BEOL

Patent metadata

Field	Value
Publication number	US-11877458-B2
Application number	US-202016813166-A
Country	US
Kind code	B2
Filing date	Mar 9, 2020
Priority date	Mar 9, 2020
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.

First claim

We claim:

1. A Resistive Random-Access Memory (RRAM) comprising:
an internal electrode;
a high k dielectric layer surrounding and in contact with the internal electrode, the high k dielectric layer having an external dielectric side not in contact with the internal electrode;
a lower substrate;
a trench having two or more trench sides, the trench disposed in the lower substrate, the internal electrode and the high k dielectric layer being disposed within the trench and the internal electrode and the high k dielectric layer protruding a protrusion distance above the lower substrate;
an upper substrate disposed on the lower substrate and disposed over at least part of the internal electrode and high k dielectric layer protruding the protrusion distance above the lower substrate and into the upper substrate; and
an interconnect within the lower substrate, the interconnect having an interconnect top, and interconnect bottom, and an interconnect side, the interconnect side being part of one of the trench sides,

wherein the interconnect side is in contact with the external dielectric side of the high k dielectric layer within the trench, and
wherein the protrusion distance is large enough so the internal electrode and the high k dielectric layer protrude through the upper substrate.

2. A RRAM, as in claim 1 , where the internal electrode is made from one or more of the following: Titanium Nitride (TiN), Tantalum Nitride (TaN), a metal, copper (Cu), aluminum (Al), and tungsten (W).

3. A RRAM, as in claim 1 , where the high k dielectric layer is made from one or more of the following: a high-k dielectric material, Hafnium Oxide (HfO x ), Tantalum Oxide (TaO x ), Aluminum Oxide (Al 2 O 3 ), Zirconium Oxide (ZrOx), and Titanium Oxide (TiO x ).

4. A RRAM, as in claim 1 , the interconnect side is in contact with the external dielectric side of the high k dielectric layer through an external electrode disposed between the interconnect side and the high k dielectric layer.

5. A RRAM, as in claim 4 , where the external electrode surrounds the high k dielectric layer and is in electrical contact with the interconnect side and the high k dielectric layer.

6. A RRAM, as in claim 1 , where an interconnect via protrudes through the upper substrate to make contact with the interconnect.

7. A RRAM, as in claim 1 , further comprising an external electrode disposed between the interconnect side and the high k dielectric layer, the external electrode forming an electrical connection between the high k dielectric layer and the interconnect side.

8. A dual Resistive Random-Access Memory (RRAM) comprising:
an internal electrode;
a high k dielectric layer surrounding and in contact with the internal electrode, the high k dielectric layer having an external dielectric side not in contact with the internal electrode, the high k dielectric layer further having a first dielectric side and a second dielectric side;
a lower substrate;
an upper substrate disposed on the lower substrate;
a trench having a first trench side and a second trench side, the trench passing through the upper substrate and disposed in the lower substrate;
a first interconnect within the lower substrate, the interconnect having a first interconnect side;
a second interconnect within the lower substrate, the second interconnect having a second interconnect side, the trench being between the first interconnect side and the second interconnect side, the first interconnect side being part of the first trench side, and the second interconnect side being part of the second trench side, and the first interconnect side and the second interconnect side not being electrically connected,

wherein the internal electrode and the high k dielectric layer are disposed within the trench and the external dielectric side of the first dielectric side of the dielectric layer is electrically and physically connected to first interconnect side and the external dielectric side of the second dielectric side of the dielectric layer is electrically and physically connected to the second interconnect side.

9. A dual RRAM, as in claim 8 , further comprising:
a first external electrode electrically and physically connects the first interconnect side and the external dielectric side of the first dielectric side of the dielectric layer; and
a second external electrode electrically and physically connects the second interconnect side and the external dielectric side of the second dielectric side of the dielectric layer,

wherein the first external electrode and the second external electrode are not electrically connected.

Assignees

• IBM

Inventors

• Li Baozhen
• Yang Chih-Chao
• Linder Barry
• Narayanan Vijay

Classifications

• H10B63/80 Primary

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10N70/066

  by filling of openings, e.g. damascene method · CPC title

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title