Scalable silicon based resistive memory device

Patent metadata

Field	Value
Publication number	US-10290801-B2
Application number	US-201514613585-A
Country	US
Kind code	B2
Filing date	Feb 4, 2015
Priority date	Feb 7, 2014
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A memory cell that includes a first metal layer formed over a substrate is provided. The substrate includes one or more complementary metal-oxide semiconductor devices. The memory cell also includes a via device that connects at least a portion of the first metal layer and at least another portion of a second metal layer. The first metal layer has a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device. The memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device.

First claim

What is claimed is:

1. A memory device, comprising:
a first metal layer formed over a substrate comprising one or more complementary metal-oxide semiconductor devices; and
a via device that contacts at least a portion of the first metal layer and that contacts or electrically contacts at least another portion of a second metal layer, wherein the first metal layer comprises a first thickness having an edge thereof that serves as an electrode for a memory cell formed by the via device, wherein the memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory device, wherein the via device is filled at least in part with a switch layer liner and with a material selected from a group consisting essentially of: Al, Al and Cu, Al with TiN, Al with Ti or TiN, TiN, Al and Cu or TiN, a suitable compound of Al, Cu or Ti, and a suitable alloy of Al, Cu, or Ti, the material serving as a second electrode for the memory cell formed by the via device, wherein the minimum feature size of the memory device is as large as 248 nanometers and the memory cell scales at least to a 20 nanometer device.

2. The memory device of claim 1 , wherein the memory cell scales to a limit defined at least in part by a dimension of the via device.

3. The memory device of claim 1 , wherein the memory cell scales to a limit defined by the first thickness equal to about 5 nanometers.

4. The memory device of claim 1 , wherein the via device is further filled with at least one select layer liner, and wherein the select layer liner or the switch layer liner is formed of a material selected from a group consisting of: SiOx, SiOx with TiOx, SiOx with AlOx, TiOx, AlOx, or a suitable combination thereof.

5. The memory device of claim 1 , wherein the via device comprises a collar that comprises conducting material.

6. The memory device of claim 1 , wherein the first metal layer is formed of a material selected from W, Al, Cu, TaN, Ti, TiN, W—Ti, or a suitable combination thereof and the second metal layer is formed of a material selected from a group consisting of: W, Al, Cu, TaN, Ti, TiN, W—Ti, or a suitable combination thereof.

7. A memory device, comprising:
a substrate that comprises one or more complementary metal-oxide semiconductor devices;
a first metal layer formed over the substrate; and
a via device that contacts at least a portion of the first metal layer and that contacts or electrically contacts at least another portion of a second metal layer, wherein the first metal layer comprises a first thickness having an edge thereof that operates as an electrode for a memory cell formed by the via device, and wherein the memory cell scales as a function of the first thickness and at least in part independent of a minimum feature size of the memory cell, wherein the via device is filled at least in part with a resistive switching material liner and with a material selected from a group consisting essentially of: Al, Al and Cu, Al with TiN, Al with Ti or TiN, TiN, Al and Cu or TiN, a suitable compound of Al, Cu or Ti, and a suitable alloy of Al, Cu, or Ti, the material serving as a second electrode for the memory cell formed by the via device, wherein the memory cell scales to a limit defined by the first thickness equal to about 5 nanometers.

8. The memory device of claim 7 , wherein the limit defined by the first thickness is further defined at least in part by a dimension of the via device.

9. The memory device of claim 7 , wherein another minimum feature size of an integrated circuit fabrication equipment is no larger than 248 nanometers, and the memory cell scales to the first thickness equal to about 5 nanometers.

10. The memory device of claim 7 , wherein the via device is filled in further part with a select layer liner.

11. The memory device of claim 7 , wherein the via device comprises a collar that comprises conducting material.

12. A memory device, comprising:
a via formed within an insulating material between a first metal layer of an integrated circuit and a second metal layer of the integrated circuit, the via exposing a surface of the first metal layer through the insulating material;
a via liner material deposited as a thin film with a relatively uniform thickness over a surface of the insulating material exposed by the via, the via liner material is an electrically resistive material having a molecular structure selected to facilitate trapping of conductive particles within the via liner material at a potential lower in magnitude than a program potential for the memory device, wherein the via liner material comprises at least one select layer and at least one switch layer;
a fill material deposited over the via liner and over the via formed within the insulating material, the fill material comprising the conductive particles for which the electrically resistive material facilitates the trapping within the molecular structure of the via liner at the potential lower in magnitude than the program potential; and
a contact material that provides electrical continuity between the fill material and the second metal layer.

13. The memory device of claim 12 , wherein the at least one switch layer of the via liner material is a material selected from a group consisting of: SiOx, SiOx with TiOx, SiOx with AlOx, TiOx, AlOx, and a suitable combination thereof.

14. The memory device of claim 12 , wherein the fill material is a material selected from a group consisting essentially of: Al, Al and Cu, Al with TiN, Al with Ti or TiN, TiN, Al and Cu or TiN, suitable compounds of Al, Cu or Ti, and suitable alloys of Al, Cu, or Ti.

15. The memory device of claim 12 , wherein the fill material comprises at least two materials arranged along a direction at least in part perpendicular to the surface of the first metal layer exposed through the insulating material.

16. The memory device of claim 12 , wherein a portion of the via liner or a portion of the fill material serves as a collar in orientation to the via formed within the insulating material and to a second portion of the via liner or the fill material within the via, the portion having a larger width relative to the second portion.

17. The memory device of claim 1 , further comprising a conductive plug of material coupled to the via device and to the other portion of the second metal layer.

18. The memory device of claim 7 , further comprising a conductive plug in contact with the second electrode of the memory cell and the second metal layer, wherein the via device electrically contacts the second metal layer by way of the conductive plug.

19. The memory device of claim 7 , wherein the via device intersects the first metal layer, and the first thickness of the first metal layer defines a contact area between the electrode and a switching material of the memory cell.

20. The memory device of claim 12 , wherein the via liner material is deposited in contact with the surface of the first metal layer exposed by the via through the insulating material.

Assignees

• Crossbar Inc

Inventors

• Narayanan Sundar
• Maxwell Steve
• Vasquez Jr Natividad
• Gee Harry Yue

Classifications

• H01L45/085

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/1226

  Electricity · mapped topic

• H01L45/1266

  Electricity · mapped topic

• H01L45/1233 Primary

  Electricity · mapped topic