High density resistive random access memory (RRAM)

Patent metadata

Field	Value
Publication number	US-9865653-B2
Application number	US-201615293998-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Apr 16, 2015
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars ism stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

First claim

What is claimed is:

1. A method of making a memory cell, comprising:
lithographically forming a plurality of semiconductor fins on a substrate layer in a spaced apart fashion from one another;
depositing a siliciding layer on the plurality of semiconductor fins and on the substrate layer;
annealing the siliciding layer so as to cause silication of at least a portion of each of the plurality of semiconductor fins to thereby form a plurality of silicided semiconductor fins;
depositing a first metal liner layer on the plurality of silicided semiconductor fins and on the substrate layer using chemical vapor deposition;
depositing a layer of hafnium oxide on the first metal liner layer using atomic layer deposition;
depositing a second metal liner layer on the layer of hafnium oxide using chemical vapor deposition;
filling areas between adjacent ones of the plurality of silicided semiconductor fins with a metal fill;
forming a plurality of first contact pillars on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins;
forming a second plurality of contact pillars each on the metal fill adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

2. The method of claim 1 , wherein the siliciding layer is comprised of nickel-platinum.

3. The method of claim 1 , wherein the substrate layer comprises a semiconductor layer.

4. The method of claim 2 , further comprising forming an insulating layer on the substrate layer between adjacent ones of the plurality of the semiconductor fins prior to deposition of the nickel-platinum layer; and wherein the substrate layer comprises the semiconductor layer with the insulating layer thereon.

5. The method of claim 3 , wherein the substrate layer comprises a semiconductor layer stacked on an insulating layer.

6. The method of claim 2 , wherein dimensions of the plurality of semiconductor fins, a thickness of the nickel-platinum layer, and aspects of the annealing are selected such that all of each of the plurality of semiconductor fins is fully silicided.

7. A method, comprising:
electrically coupling a first conduction terminal of a transistor to a first electrode of a resistive random access memory (RRAM) device, a second conduction terminal of the transistor to a source line, and a control terminal of the transistor to a word line;
electrically coupling a bit line to a second electrode of the RRAM device;
asserting the word line and the source line such that the transistor turns on;
setting the bit line to a read voltage threshold such that current flowing through the transistor and into the first electrode and through a first silicided semiconductor fin of the RRAM device causes formation of conductive path in a hafnium oxide layer stacked on the first silicided semiconductor fin of the RRAM device;
discharging the source line; and
resetting the bit line so as to dissolve the conductive path.

8. The method of claim 7 , wherein the conductive path comprises a conductive filament.

9. A method of making a memory cell, comprising:
forming a plurality of semiconductor fins on a substrate layer;
depositing a siliciding layer on at least the plurality of semiconductor fins;
annealing the siliciding layer so as to cause silication of at least a portion of each of the plurality of semiconductor fins to thereby form a plurality of silicided semiconductor fins;
forming, on the plurality of silicided semiconductor fins, in a stacked arrangement, a first metal liner layer, a layer of hafnium oxide, and a second metal liner layer;
filling areas between adjacent ones of the plurality of silicided semiconductor fins with a metal fill;
forming a plurality of first contact pillars adjacent a different respective one of the plurality of silicided semiconductor fins;
forming a second plurality of contact pillars each on the metal fill adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

10. The method of claim 9 , wherein the siliciding layer is comprised of nickel-platinum.

11. The method of claim 10 , further comprising forming an insulating layer on the substrate layer between adjacent ones of the plurality of the semiconductor fins prior to deposition of the nickel-platinum layer; and wherein the substrate layer comprises a semiconductor layer with the insulating layer thereon.

12. The method of claim 10 , wherein dimensions of the plurality of semiconductor fins and a thickness of the nickel-platinum layer are selected such that all of each of the plurality of semiconductor fins is fully silicided.

13. The method of claim 9 , wherein the substrate layer comprises a semiconductor layer stacked on an insulating layer.

14. The method of claim 9 , wherein each of the plurality of semiconductor fins is formed to have a width of between six and twelve nanometers and a pitch of twenty five to forty five nanometers; and wherein a spacing between adjacent semiconductor fins of the plurality thereof is between fifteen and thirty five nanometers.

15. The method of claim 9 , wherein a top of the metal fill layer is recessed below a top of each of the plurality of semiconductor fins by ten to twenty nanometers.

Assignees

• St Microelectronics Inc

Inventors

• Liu Qing
• Zhang John Hongguang

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H01L27/2436 Primary

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/1616

  Electricity · mapped topic