3D printed semiconductor package

US11869925B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11869925-B2
Application numberUS-202117163766-A
CountryUS
Kind codeB2
Filing dateFeb 1, 2021
Priority dateDec 28, 2018
Publication dateJan 9, 2024
Grant dateJan 9, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In described examples, a method for fabricating a semiconductor device and a three dimensional structure, and packaging them together, includes: fabricating the integrated circuit on a substrate, immersing the substrate in a liquid encapsulation material, and illuminating the liquid encapsulation material to polymerize the liquid encapsulation material. Immersing the semiconductor device is performed to cover a layer of a platform in the liquid encapsulation material. The platform is a lead frame, a packaging substrate, or the substrate. The illuminating step targets locations of the liquid encapsulation material covering the layer. Illuminated encapsulation material forms solid encapsulation material that is fixedly coupled to contiguous portions of the semiconductor device and of the solid encapsulation material. The immersing and illuminating steps are repeated until a three dimensional structure is formed. The integrated circuit and the three dimensional structure are encapsulated in a single package.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: immersing a substrate including at semiconductor die attached thereon in a liquid polymer material: irradiating part of the liquid polymer material to polymerize and to form a three- dimensional polymer structure on the substrate; coating the three-dimensional polymer structure with a metal to form a device; electrically connecting the device with the semiconductor die; and forming an integrated circuit by encapsulating the semiconductor die and the three- dimensional polymer structure in a package. 2. The method of claim 1 , wherein the three-dimensional polymer structure is formed in layers of the polymerized liquid polymer material by moving the substrate relative to a source of irradiation. 3. The method of claim 1 , further comprising annealing the metal to electrically connect the device with the integrated circuit. 4. The method of claim 1 , wherein the encapsulating includes vat polymerization. 5. The method of claim 1 , a wherein the liquid polymer material includes a catalyst selected to facilitate the coating. 6. The method of claim I, wherein the device includes an inductor. 7. The method of claim 1 , wherein the device includes an antenna. 8. The method of claim 1 , wherein encapsulating the integrated circuit and the three-dimensional polymer structure in a package comprises forming a cavity around at least a part of the device. 9. The method of claim 1 , further comprising coating the metal with an insulator. 10. A method comprising: immersing a substrate in a liquid polymer material in a container, the container having a bottom, the substrate further including a semiconductor die attached thereon; irradiating part of the liquid polymer material via the bottom of the container to polymerize and to form a three-dimensional polymer structure on the substrate; separating the three-dimensional polymer structure from a surface of the bottom of the container; and encapsulating the semiconductor die and the three-dimensional polymer structure in a package to form an integrated circuit. 11. The method of claim 10 , wherein the surface of the bottom of the container includes at least one of: an oxygen permeable glass. or a polymerization inhibitor. 12. The method of claim 10 , further comprising coating the three-dimensional polymer structure with a metal to form a device. 13. The method of claim 12 , wherein the device includes an inductor. 14. The method of claim 12 , wherein the device includes an antenna. 15. The method of claim 10 , wherein encapsulating the integrated circuit and the three-dimensional polymer structure in a package comprises forming a cavity around at least a part of the polymer three-dimensional structure. 16. The method of claim 10 , wherein the three-dimensional polymer structure is formed in layers of the polymerized liquid polymer material by moving the substrate relative to a source of irradiation.

Assignees

Inventors

Classifications

  • for antennas · CPC title

  • the semiconductor body being completely enclosed · CPC title

  • Manufacture or treatment · CPC title

  • at high-frequency [HF] or radio frequency [RF] · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

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Frequently asked questions

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What does patent US11869925B2 cover?
In described examples, a method for fabricating a semiconductor device and a three dimensional structure, and packaging them together, includes: fabricating the integrated circuit on a substrate, immersing the substrate in a liquid encapsulation material, and illuminating the liquid encapsulation material to polymerize the liquid encapsulation material. Immersing the semiconductor device is per…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H10D1/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 09 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).