IC having a metal ring thereon for stress reduction

Patent metadata

Field	Value
Publication number	US-11869820-B2
Application number	US-202217810568-A
Country	US
Kind code	B2
Filing date	Jul 1, 2022
Priority date	Dec 12, 2019
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.

First claim

The invention claimed is:

1. A method of fabricating an integrated circuit (IC), comprising:
providing a substrate including circuitry configured for a function including a stress sensitive circuit portion; and
forming a solid same metal wall that is ring-shaped having opposing end surfaces, one of the end surfaces attached to the substrate and the other end surface attached to a metal pad that covers the entire other end surface, wherein the stress sensitive circuit portion is positioned with a least a majority of its area within an inner area of the substrate that is framed by the solid metal wall to provide a cavity.

2. The method of claim 1 , wherein the function the circuitry implements comprises that of an amplifier, an analog to digital converter (ADC), a digital to analog converter (DAC), a voltage reference, a sensor for sensing a physical parameter, or a micro-electromechanical system (MEMS) device including at the sensor for sensing the physical parameter.

3. The method of claim 1 , wherein a width of the metal wall is between 10 μm and 200 μm.

4. The method of claim 1 , wherein the stress sensitive circuit portion comprises an environmental sensor for sensing a physical parameter.

5. The method of claim 1 , further comprising:
forming a leadframe including leads or lead terminals,
forming a pad, wherein one of the opposing end surfaces is coupled to the substrate and another of the opposing end surfaces is coupled to the pad, and
molding to form a mold compound to provide encapsulation for a packaged device, wherein at least a portion of the mold compound is excluded from being inside the solid same metal wall.

6. The method of claim 5 , wherein the coupling the opposing end surfaces to the substrate and to the pad comprises flipchip bonding the opposing end surfaces to the leads or to the lead terminals.

7. The method of claim 1 , further including covering the IC with a mold compound, wherein at least a portion of the mold compound is excluded from being inside the continuous metal wall.

8. The method of claim 1 , further including an opening though the leadframe for exposing the cavity to an environment.

9. The method of claim 1 , further including a lid for sealing the cavity.

10. A method of fabricating an integrated circuit (IC), comprising:
forming a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion; and
forming a continuous solid same metal wall that is ring-shaped having opposing end surfaces, one of the end surfaces attached to the substrate and the other end surface attached to a metal pad that covers the entire other end surface, wherein the stress sensitive circuit portion is positioned with at least a majority of its area within an inner area of the substrate that is framed by the continuous metal wall to provide a cavity.

11. The method of claim 10 , wherein the function the circuitry implements comprises that of an amplifier, an analog to digital converter (ADC), a digital to analog converter (DAC), a voltage reference, an environmental sensor for sensing a physical parameter, or a micro-electromechanical system (MEMS) device including at least the sensor for sensing the physical parameter.

12. The method of claim 10 , wherein a width of the metal wall is between 10 μm and 200 μm.

13. The method of claim 10 , wherein the stress sensitive circuit portion comprises an environmental sensor for sensing a physical parameter.

14. The method of claim 10 , wherein the at least one stress sensitive circuit portion comprises a first stress sensitive portion and at least a second stress sensitive portion.

15. The method of claim 10 , wherein the ring-shaped comprises a circular shape.

16. The method of claim 10 , wherein the stress sensitive circuit portion is positioned entirely within the inner area.

17. A method of fabricating a packaged device, comprising:
forming an integrated circuit (IC), comprising:
forming a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer, wherein there are bonding features on the bond pads, wherein the stress sensitive circuit portion comprises an environmental sensor for sensing a physical parameter, and wherein the leadframe has an opening though the leadframe configured so that the stress sensitive circuit portion is exposed to an environment;
forming a continuous metal wall that is ring-shaped positioned above the top metal layer that is not electrically coupled to the circuitry;
wherein the stress sensitive circuit portion is positioned with at least a majority of its area within an inner area of the substrate that is framed by the continuous metal wall to provide a cavity;

providing a leadframe including leads or lead terminals;
wherein the bonding features are bonded to the leads or to the lead terminals; and
covering the IC with a mold compound, wherein at least a portion of the mold compound is excluded from being inside the continuous metal wall.

18. The method of claim 17 , wherein the function the circuitry implements comprises that of an amplifier, an analog to digital converter (ADC), a digital to analog converter (DAC), a voltage reference, a sensor for sensing a physical parameter, or a micro-electromechanical system (MEMS) device including at the sensor for sensing the physical parameter.

19. The method of claim 17 , wherein the bonding features are flipchip bonded to the leads or to the lead terminals.

20. A method of fabricating a packaged device, comprising:
forming an integrated circuit (IC), comprising:
forming a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer, wherein there are bonding features on the bond pads;
forming a continuous metal wall that is ring-shaped positioned above the top metal layer that is not electrically coupled to the circuitry;
wherein the stress sensitive circuit portion is positioned with at least a majority of its area within an inner area of the substrate that is framed by the continuous metal wall to provide a cavity;

providing a leadframe including leads or lead terminals;
wherein the stress sensitive circuit portion comprises an environmental sensor for sensing a physical parameter, and wherein the leadframe has opening configured so that the stress sensitive circuit portion is exposed to an environment;
wherein the bonding features are bonded to the leads or to the lead terminals; and
covering the IC with a mold compound, wherein at least a portion of the mold compound is excluded from being inside the continuous metal wall.

21. A method of fabricating a packaged device, comprising:
forming an integrated circuit (IC), comprising:
forming a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer, wherein there are bonding features on the bond pads;
forming a continuous metal wall that is ring-shaped positioned above the top metal layer that is not electrically coupled to the circuitry;
wherein the stress sensitive circuit portion is posit

Assignees

• Texas Instruments Inc

Inventors

• Nangia Amit Sureshkumar
• Koduri Sreenivasan Kalyani
• Gurrum Siva Prakash
• Manack Christopher Daniel

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title