Transistor DV/DT control circuit

Patent metadata

Field	Value
Publication number	US-11855635-B2
Application number	US-202217853740-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jun 30, 2021
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Circuits and methods that control a rate of change of a drain voltage as a function of time in a transistor are disclosed. In one aspect, the circuit includes a transistor having a gate terminal that controls operation of the transistor, and a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and further arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, where the first rate is different than the second rate.

First claim

What is claimed is:

1. A circuit comprising:
a first transistor having a first gate terminal, a first source terminal and a first drain terminal;
a second transistor having a second gate terminal, a second source terminal and a second drain terminal, the second drain terminal coupled to the first gate terminal;
a control circuit coupled to the second gate terminal and arranged to change a conductive state of the second transistor in response to receiving an input signal; and
an impedance element coupled in series to the second transistor;
a detection circuit coupled to the first gate terminal;
a third transistor having a third gate terminal, a third source terminal and a third drain terminal;
a sensing circuit coupled to the impedance element and arranged to sense an impedance value of the impedance element; and
a current sink coupled to the second source terminal and to the sensing circuit;
wherein the detection circuit is coupled to the third gate terminal and the third drain terminal is coupled to the first gate terminal; and
wherein the detection circuit is arranged to sense a voltage at the first gate terminal, and in response to the voltage at the first gate terminal reaching a value below a threshold voltage, change a state of the third transistor to a conductive state.

2. The circuit of claim 1 , wherein the first transistor comprises gallium nitride (GaN).

3. The circuit of claim 2 , wherein the second transistor comprises silicon.

4. The circuit of claim 2 , wherein the second transistor is disposed in a silicon-based substrate, and the impedance element is disposed adjacent to the silicon-based substrate.

5. The circuit of claim 1 , wherein the sensing circuit is arranged to set a value for a discharge current flowing through the current sink corresponding to a sensed impedance value of the impedance element.

6. A circuit comprising:
a transistor including a gate terminal that controls operation of the transistor;
a control circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and arranged to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage;
a sense circuit coupled to a drain terminal of the transistor and arranged to sense a voltage at the drain terminal of the transistor; and
a current mirror circuit coupled to the sense circuit;
wherein the control circuit is coupled to the current mirror circuit.

7. The circuit of claim 6 , wherein the first rate is different than the second rate.

8. The circuit of claim 7 , wherein the control circuit is further arranged to change the voltage at the gate terminal at a third rate of voltage with respect to time from the second intermediate voltage to a second voltage.

9. The circuit of claim 8 , wherein the first voltage is an on-state voltage of the transistor that enables current to flow through the transistor and the second voltage is an off-state voltage of the transistor that prevents current from flowing through the transistor.

10. The circuit of claim 6 , wherein the first rate is greater than the second rate.

11. The circuit of claim 6 , further comprising a first pull-down transistor having a first gate terminal, a first drain terminal and a first source terminal, and a second pull-down transistor having a second gate terminal, a second drain terminal and a second source terminal, wherein the first and second drain terminals are coupled to the gate terminal, and wherein the control circuit is coupled to the first and second gate terminals, and arranged to control a conductivity state of the first and second pull-down transistors.

12. A circuit comprising:
a transistor including a gate terminal that controls operation of the transistor;
a control circuit coupled to the gate terminal and arranged to allow a discharge current to flow from the gate terminal at a first current rate during a first time period, and to allow the discharge current to flow from the gate terminal at a second current rate during a second time period, and to allow the discharge current to flow from the gate terminal at the first current rate during a third time period;
a sense circuit coupled to a drain terminal of the transistor and arranged to sense a voltage at the drain terminal of the transistor; and
a current mirror circuit coupled to the sense circuit;
wherein the control circuit is coupled to the current mirror circuit.

13. The circuit of claim 12 , wherein the first current rate is greater than the second current rate.

14. The circuit of claim 12 , further comprising a first pull-down transistor having a first gate terminal, a first drain terminal and a first source terminal, and a second pull-down transistor having a second gate terminal, a second drain terminal and a second source terminal, wherein the first and second drain terminals are coupled to the gate terminal, and wherein the control circuit is coupled to the first and second gate terminals, and arranged to control a conductivity state of the first and second pull-down transistors.

15. The circuit of claim 14 , wherein the first pull-down transistor and the second pull-down transistor are arranged, in combination, to allow the discharge current to flow at the first current rate.

Assignees

• Navitas Semiconductor Ltd

Inventors

• Jia Hongwei
• Sharma Santosh
• Kinzer Daniel M
• Sinow Victor
• Topp Matthew Anthony

Classifications

• H03K3/012 Primary

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• Y02B70/10

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