Method and circuit to isolate body capacitance in semiconductor devices

Patent metadata

Field	Value
Publication number	US-11855590-B2
Application number	US-202218081513-A
Country	US
Kind code	B2
Filing date	Dec 14, 2022
Priority date	Nov 15, 2018
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

First claim

What is claimed is:

1. An amplifying circuit, comprising:
a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein
a source terminal and a body terminal of the first transistor are coupled together through a first resistor,
the source terminal and the body terminal of the first transistor are also coupled together through a first diode, and
a drain terminal and the body terminal of the first transistor are coupled together through a second diode, and

a common-source (CS) amplifier, wherein the CS amplifier comprises a second transistor, wherein a source terminal and a body terminal of the second transistor are coupled directly to each other, and wherein the source terminal of the first transistor is coupled directly to a drain terminal of the second transistor, wherein the second transistor is further configured to receive an input voltage at a gate terminal of the CS amplifier.

2. The amplifying circuit of claim 1 , wherein
the first diode is formed between an N region of the source terminal of the first transistor and a P-well region in which the body terminal of the first transistor is fabricated; and
the second diode is formed between an N region of the drain terminal of the first transistor and the P-well region.

3. The amplifying circuit of claim 1 , wherein the first transistor comprises one of the following: an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type MOS (PMOS) transistor.

4. The amplifying circuit of claim 1 , wherein the first transistor further comprises:
a gate insulator; and
a conductive gate formed on top of the gate insulator.

5. The amplifying circuit of claim 1 , wherein the CG amplifier is fabricated in a deep N well of a P-type substrate.

6. The amplifying circuit of claim 1 , wherein the CG amplifier is fabricated in a P well of an N-type substrate.

7. The amplifying circuit of claim 1 ,
wherein the second transistor is further configured to receive the input voltage at the gate terminal of the CS amplifier through a capacitor.

8. A power amplifying circuit, comprising:
a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein
source terminal and body terminal of the first transistor are coupled together through a first resistor,
the source terminal and the body terminal of the first transistor are also coupled together through a first diode,
drain terminal and the body terminal of the first transistor are coupled together through a second diode, and
the body terminal of the first transistor is coupled to ground; and

a common-source (CS) amplifier, wherein the CS amplifier comprises a second transistor that is connected in series with the first transistor.

9. The power amplifying circuit of claim 8 , wherein the first and second transistors each comprises one of the following: an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type MOS (PMOS) transistor.

10. The power amplifying circuit of claim 8 , wherein the second transistor is further configured to receive an input voltage at a gate terminal of the CS amplifier through a capacitor.

11. The power amplifying circuit of claim 10 , wherein the gate terminal of the second transistor is coupled to an input voltage through a capacitor and is further coupled to an external bias voltage through a second resistor.

12. The power amplifying circuit of claim 8 , wherein the first transistor further comprises:
a gate insulator; and
a conductive gate formed on top of the gate insulator.

13. The power amplifying circuit of claim 8 , wherein the CG amplifier is fabricated in a deep N well of a P-type substrate.

14. The power amplifying circuit of claim 8 , wherein the CG amplifier is fabricated in a P well of an N-type substrate.

15. A method of making an amplifying circuit, comprising:
forming a common-gate (CG) amplifier in a substrate, wherein the CG amplifier comprises a first transistor, wherein
a source terminal and a body terminal of the first transistor are coupled together through a first resistor,
the source terminal and the body terminal of the first transistor are also coupled together through a first diode, and
a drain terminal and the body terminal of the first transistor are coupled together through a second diode,

forming a common-source (CS) amplifier in the substrate, wherein the CS amplifier comprises a second transistor, wherein a source terminal and a body terminal of the second transistor are coupled directly to each other, and wherein the source terminal of the first transistor is coupled directly to drain terminal of the second transistor.

16. The method of claim 15 , wherein:
the first diode is formed between an N region of the source terminal of the first transistor and a P-well region in which the body terminal of the first transistor is fabricated; and
the second diode is formed between an N region of the drain terminal of the first transistor and the P-well region.

17. The method of claim 15 , wherein the first transistor comprises one of the following: an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type MOS (PMOS) transistor.

18. The method of claim 15 , wherein the first transistor further comprises:
a gate insulator; and
a conductive gate formed on top of the gate insulator.

19. The method of claim 15 , wherein the CG amplifier is fabricated in a P well of an N-type substrate.

20. The method of claim 19 , wherein the second transistor is further configured to receive an input voltage at the gate terminal of the CS amplifier through a capacitor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liang Garming
• Chai Simon
• Yeh Tzu-Jin
• Yeh En-Hsiang
• Chen Wen-Sheng

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H03F3/211 Primary

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H01L27/0629

  Electricity · mapped topic

• H01L27/0928

  Electricity · mapped topic