Enhanced base die heat path using through-silicon vias

Patent metadata

Field	Value
Publication number	US-11854935-B2
Application number	US-202016794789-A
Country	US
Kind code	B2
Filing date	Feb 19, 2020
Priority date	Feb 19, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

First claim

What is claimed is:

1. A package comprising:
a first die with a first side and a second side opposite the first side;
a second die with a first side and a second side opposite the first side, wherein the first side of the first die is coupled with the second side of the second die;
a thermal block with a first side and a second side opposite the first side, wherein the second side of the thermal block is thermally coupled with the first side of the first die, wherein the thermal block is laterally spaced apart from the second die; and
wherein the thermal block is to thermally couple the first side of the first die to the first side of the thermal block.

2. The package of claim 1 , wherein the thermal block includes one or more thermal conductivity features extending from the first side of the thermal block to the second side of the thermal block to thermally couple the first side of the thermal block with the second side of the thermal block.

3. The package of claim 2 , wherein the one of the one or more thermal conductivity features include a selected one of copper, solder, tin, silver, or gold.

4. The package of claim 2 , wherein the one or more thermal conductivity features at the second side of the thermal block are aligned, respectively, with one or more heat sources in the first die.

5. The package of claim 2 , wherein the one or more thermal conductivity features are vias filled with thermally conductive material.

6. The package of claim 1 , wherein the thermal block is a selected one of: a die, a dummy die, or a molding.

7. The package of claim 1 , wherein the first die includes one or more thermal conductivity features extending to the first side of the first die and thermally coupling with the second side of the thermal block, wherein heat within the first die is to flow via the one or more thermal conductivity features to the thermal block.

8. The package of claim 7 , wherein the one or more thermal conductivity features of the first die are within a silicon area of the first die.

9. The package of claim 1 , wherein the thermal block is a first thermal block; and further comprising:
a second thermal block with a first side and a second side opposite the first side, wherein the second side of the second thermal block is thermally coupled with the first side of the first die; and
wherein the second thermal block is to thermally couple the first side of the first die to the first side of the second thermal block.

10. The package of claim 1 , further comprising: a heat spreader thermally coupled with the first side of the thermal block.

11. The package of claim 10 , further comprising a thermal interface material between the heat spreader and the first side of the thermal block to facilitate thermal conductivity between the heat spreader in the first side of the thermal block.

12. A method comprising:
coupling a first side of a first die that has a second side opposite the first side with a second side of a second die that has a first side opposite the second side;
coupling a thermal block to the first side of the first die, wherein the thermal block includes one or more thermal conductivity features to thermally couple the first side of the thermal block with the second side of the thermal block, wherein the thermal block is laterally spaced apart from the second die.

13. The method of claim 12 , wherein the one or more thermal conductivity features include through silicon vias (TSVs).

14. The method of claim 13 , wherein the one or more thermal conductivity features are vias filled with thermally conductive material.

15. The method of claim 14 , wherein the thermally conductive material includes a selected one of copper, solder, tin, silver, or gold.

16. A system comprising:
a substrate;
a first side of a first die with the second side opposite the first side coupled to the substrate;
a second die with a first side and a second side opposite the first side, wherein the first side of the first die is coupled with the second side of the second die;
a thermal block with a first side and a second side opposite the first side, wherein the second side of the thermal block is thermally coupled with the first side of the first die, wherein the thermal block is laterally spaced apart from the second die; and
wherein the thermal block is to thermally couple the first side of the first die to the first side of the thermal block.

17. The system of claim 16 , further comprising a heat spreader thermally coupled with the first side of the thermal block and substantially surrounding the first die and the second die.

18. The system of claim 16 , wherein the heat spreader is thermally coupled with the first side of the second die.

19. The system of claim 18 , further comprising a thermal interface material between the heat spreader and the first side of the thermal block to facilitate thermal conductivity between the heat spreader in the first side of the thermal block.

20. The system of claim 17 , wherein the thermal block is a first thermal block; and further comprising:
a second thermal block with a first side and a second side opposite the first side, wherein the second side of the second thermal block is thermally coupled with the first side of the first die; and
wherein the first side of the second thermal block is thermally coupled with the heat spreader.

Assignees

• Intel Corp

Inventors

• Bertrand Weston
• Arrington Kyle
• Devasenathipathy Shankar
• Mccann Aaron
• Neal Nicholas
• Wan Zhimin

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W40/22 Primary

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title