Thermally conductive wafer layer

Patent metadata

Field	Value
Publication number	US-11854933-B2
Application number	US-202017138541-A
Country	US
Kind code	B2
Filing date	Dec 30, 2020
Priority date	Dec 30, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a semiconductor substrate having opposite first and second surfaces, the first surface having a patterned region;
circuitry in the patterned region of the first surface;
a metallic layer on the second surface; and
a carbon layer on the metallic layer.

2. The integrated circuits of claim 1 , wherein the metallic layer includes a transition metal, the transition metal including at least one of: silver, nickel, ruthenium, cobalt, molybdenum, or iridium.

3. The integrated circuits of claim 1 , wherein the carbon layer includes interior grain boundaries.

4. The integrated circuit of claim 1 , wherein the metallic layer includes a layer of metallic nanoparticles and carbon particles.

5. The integrated circuit of claim 4 , wherein the metallic nanoparticles are between 4 mn and 150 mn in diameter.

6. The integrated circuit of claim 1 , wherein the carbon layer includes a graphene layer.

7. The integrated circuit of claim 1 , wherein the carbon layer includes less than ten atomic layers.

8. The integrated circuit of claim 1 , further comprising a dielectric layer between the second surface and the metallic layer.

9. The integrated circuit of claim 8 , wherein a thickness of the dielectric layer is less than one nanometer.

10. An integrated circuit, comprising:
a semiconductor substrate having opposite first and second surfaces, the first surface having a patterned region;
circuitry in the patterned region of the first surface; and
a layer of metallic nanoparticles and carbon particles on the second surface.

11. The integrated circuits of claim 10 , wherein the metallic nanoparticles include a transition metal, the transition metal including at least one of: silver, nickel, ruthenium, cobalt, molybdenum, or iridium.

12. The integrated circuit of claim 10 , wherein the metallic nanoparticles are between 4 nm and 150 nm in diameter.

13. The integrated circuit of claim 10 , further comprising a carbon layer on the layer of metallic nanoparticles and carbon particles.

14. The integrated circuit of claim 13 , wherein the carbon layer includes a graphene layer.

15. The integrated circuit of claim 13 , wherein the carbon layer includes less than ten atomic layers.

16. The integrated circuit of claim 10 , further comprising a dielectric layer between the second surface and the layer of metallic nanoparticles and carbon particles.

17. The integrated circuit of claim 16 , wherein a thickness of the dielectric layer is less than one nanometer.

Assignees

• Texas Instruments Inc

Inventors

• Cook Benjamin Stassen
• Dadvand Nazila
• Venugopal Archana
• Revier Daniel Lee

Classifications

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W40/258

  Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title