Self-enclosed asymmetric interconnect structures

Patent metadata

Field	Value
Publication number	US-9960110-B2
Application number	US-201113976456-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The techniques provided are particularly useful, for instance, when lithography registration errors cause neighboring conductive features to be physically closer than expected, but can also he used when such proximity is intentional. In some embodiments, the techniques can be implemented using a layer of electromigration management material (EMM) and one or more insulator layers, wherein the various layers are provisioned to enable a differential etch rate. In particular, the overall etch rate of materials above the target landing pad is faster than the overall etch rate of materials above the off-target landing pad, which results in a self-enclosed conductive interconnect feature having an asymmetric taper or profile. The differential etch rate may result, for example, from configuration of the EMM layer, or from accompanying insulator layers having different etch rates.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first insulator structure having a metal feature therein;
a second insulator structure having a metal feature therein, wherein the second insulator structure is a single layer having no discernible interface within the single layer;
an intervening layer distinct from and between the first and second insulator structures, the intervening layer having a relatively lower etch rate for a given etchant than the second insulator structure, the intervening layer including a convex protrusion, wherein the first insulator structure, the intervening layer, and the second insulator structure are arranged in a vertical stack; and
a conductive interconnect feature connecting the metal feature of the first insulator structure to the metal feature of the second insulator structure, the conductive interconnect feature passing through both the intervening layer and the second insulator structure in at least one horizontal common plane, wherein the conductive interconnect feature includes an asymmetric taper that causes a concave depression on only one side of the conductive interconnect feature, wherein the concave depression tapers towards an opposing side of the conductive interconnect feature to cause the conductive interconnect feature to at least partially land on the metal feature of the first insulator structure, and wherein the concave depression of the conductive interconnect feature is conformal to the convex protrusion of the intervening layer.

2. The device of claim 1 wherein the conductive interconnect feature only partially lands on the metal feature of the first insulator structure and wherein material of the second insulator structure is on a remainder of the metal feature of the first insulator structure.

3. The device of claim 1 wherein the intervening layer:
is not present over the metal feature of the first insulator structure; or
has a variable thickness such that the intervening layer is thinner at a position on the metal feature of the first insulator structure relative to the intervening layer at a position on the first insulator structure.

4. The device of claim 1 wherein the intervening layer includes a high-k dielectric material.

5. The device of claim 1 wherein the intervening layer is a single layer of electromigration management material with no discernible interface within that electromigration management material layer.

6. The device of claim 1 wherein no discernible interface exists between the metal feature of the second insulator structure and the conductive interconnect feature.

7. The device of claim 1 wherein the convex protrusion is integral with another portion of the intervening layer that is on the first insulator structure.

8. The device of claim 1 wherein the intervening layer includes one or both of carbon or nitrogen.

9. The device of claim 1 wherein the second insulator structure and the intervening layer include the same material composition but the material of the second insulator structure is relatively more porous than the material of the intervening layer such that the intervening layer has a relatively lower etch rate for a given etchant than the second insulator structure.

10. The device of claim 1 wherein the intervening layer has a variable thickness in that, in sections where the intervening layer is under the second insulator structure, the intervening layer is thinner at a position on the metal feature of the first insulator structure relative to the intervening layer thickness at a position on the first insulator structure.

11. The device of claim 10 wherein the intervening layer thickness at the position on the metal feature of the first insulator structure is more than two times thinner than the intervening layer thickness at the position on the first insulator structure.

12. The device of claim 10 wherein, for the given etchant, the ratio of the etch rate of the second insulator structure material to the etch rate of the intervening layer material is greater than 2.

13. The device of claim 1 wherein, for the given etchant, the ratio of the etch rate of the second insulator structure material to the etch rate of the intervening layer material is greater than 5.

14. The device of claim 1 wherein the opposing side of the conductive interconnect feature is substantially vertical.

15. The device of claim 1 wherein the intervening layer has a uniform thickness in portions not including the convex protrusion, and wherein the intervening layer is not present over the metal feature of the first insulator structure.

16. The device of claim 1 further comprising an electromigration barrier layer between the first insulator structure and the intervening layer.

17. The device of claim 16 , wherein the electromigration barrier layer includes different material from the intervening layer.

18. The device of claim 1 wherein the first and second insulator structures include the same insulator material.

19. An electronic system comprising the device of claim 1 .

20. A multilayer integrated circuit device, comprising:
a first insulator structure having a metal feature therein;
a second insulator structure having a metal feature therein;
an electromigration barrier layer between the first and second insulator structures, the electromigration barrier layer having a relatively lower etch rate for a given etchant than the second insulator structure, the electromigration barrier layer including a convex protrusion, wherein the first insulator structure, the electromigration barrier layer, and the second insulator structure are arranged in a vertical stack, wherein the electromigration barrier layer is a single layer having no discernible interface within that electromigration barrier layer; and
a conductive interconnect feature connecting the metal feature of the first insulator structure to the metal feature of the second insulator structure, the conductive interconnect feature passing through both the electromigration barrier layer and the second insulator structure in at least one horizontal common plane, wherein the conductive interconnect feature includes an asymmetric taper that causes a concave depression on only one side of the the conductive interconnect feature, wherein the concave depression tapers towards an opposing side of the conductive interconnect feature to cause the conductive interconnect feature to only partially land on the metal feature of the first insulator structure, and wherein the concave depression of the conductive interconnect feature is conformal to the convex protrusion of the electromigration barrier layer.

21. The device of claim 20 wherein the second insulator structure is a single layer having no discernible interface within the single layer.

22. The device of claim 20 wherein the electromigration barrier layer includes one or both of carbon or nitrogen.

23. The device of claim 20 wherein the electromigration barrier layer has a variable thickness such that the electromigration barrier layer is thinner at a position on the metal feature of the first insulator structure relative to the electromigration barrier layer at a position on the first insulator structure.

24. A method for forming a semiconductor device, comprising:
providing a first insulator structure having a metal feature therein;
providing a second insulator structure having a metal feature therein, wherein the second insulator structure is a

Assignees

• Boyanov Boyan
• Intel Corp

Inventors

• Boyanov Boyan

Classifications

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title