Semiconductor structure with stacked vias having dome-shaped tips

Patent metadata

Field	Value
Publication number	US-11848264-B2
Application number	US-202117303600-A
Country	US
Kind code	B2
Filing date	Jun 3, 2021
Priority date	Jun 3, 2021
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A semiconductor structure may include a metal line, a via above and in electrical contact with the metal lines, and a dielectric layer positioned along a top surface of the metal lines. A top surface of the dielectric layer may be below the dome shaped tip of the via. A top portion of the via may include a dome shaped tip. The semiconductor structure may include a liner positioned along the top surface of the dielectric layer and a top surface of the dome shaped tip of the via. The liner may be made of tantalum nitride or titanium nitride. The dielectric layer may be made of a low-k material. The metal line and the via may be made of ruthenium. The metal line may be made of molybdenum.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first metal line;
a first via above and in electrical contact with the first metal line, wherein a top portion of the first via includes a first dome shaped tip;
a first dielectric layer positioned along a top surface of the first metal line, wherein a top surface of the first dielectric layer is below the first dome shaped tip of the first via;
a first liner positioned along the top surface of the first dielectric layer and a top surface of the first dome shaped tip of the first via; and
a second via above and in electrical contact with a second metal line, wherein a top portion of the second via includes a second dome shaped tip,
wherein the second metal line is on top of and in direct contact with the first liner; wherein the first dome shaped tip of the first via has an enlarged width that is wider than a bottom of the first dome shaped tip; and wherein a bottom of the first via is wider than the bottom of the first dome shaped tip.

2. The semiconductor structure of claim 1 , further comprising:
a second dielectric layer positioned along a top surface of the second metal line, wherein a top surface of the second dielectric layer is below the second dome shaped tip of the second via; and
a second liner positioned along the top surface of the second dielectric layer and a top surface of the second dome shaped tip of the second via.

3. The semiconductor structure of claim 2 , wherein the first and second dielectric layers are made of a low-k material.

4. The semiconductor structure of claim 1 , wherein the first and second metal lines and the first and second vias are made of ruthenium.

5. The semiconductor structure of claim 1 , wherein the first and second metal lines and the first and second vias are made of molybdenum.

Assignees

• IBM

Inventors

• Motoyama Koichi
• Cheng Kenneth Chun Kuen
• Park Chanro
• Reznicek Alexander

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title