Contacts having a geometry to reduce resistance

Patent metadata

Field	Value
Publication number	US-2017263557-A1
Application number	US-201615069439-A
Country	US
Kind code	A1
Filing date	Mar 14, 2016
Priority date	Mar 14, 2016
Publication date	Sep 14, 2017
Grant date	—

Abstract

A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dieletric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

First claim

1 . An electrical contact comprising:
a first contact portion extending through an intralevel dielectric to a semiconductor device, wherein an upper surface of the first contact portion that is opposing a surface of the first contact portion that is in contact with the semiconductor device has a planar upper surface; a second contact portion having an exterior surface defined by a curvature and a width greater than the first contact portion, wherein the curvature of the second contact portion has a greater surface area than the planar upper surface of the first contact portion; and a third contact portion in direct contact with the second contact portion that encapsulates the second contact portion.

2 . The electrical contact of claim 1 , wherein the first contact portion is a stud having sidewalls with a length substantially perpendicular to an upper surface of source and drain portions of the semiconductor device.

3 . The electrical contact of claim 2 , wherein the first contact portion comprises tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu) and combinations thereof.

4 . The electrical contact of claim 1 further comprising a liner of a metal nitride on external surfaces of the first contact portion that are not in direct contact with the second contact portion, the liner of the metal nitride positioned between the first contact portion and the intralevel dielectric material.

5 . The electrical contact of claim 4 , wherein the liner of the metal nitride comprises titanium nitride, tantalum nitride, tungsten nitride, aluminum nitride or a combination thereof.

6 . The electrical contact of claim 1 , wherein the second contact portion encapsulates and is in direct contact with an entirety of the upper most surface of the first contact portion and a portion of a sidewall of the first contact portion.

7 . The electrical contact of claim 1 , wherein the second contact portion comprises tungsten (W), cobalt (Co), ruthenium (Ru) or combinations thereof.

8 . The electrical contact of claim 7 , wherein the second contact portion is formed using a selective growth process, in which the metal for the second contact portion forms selectively to the first contact portion without forming on the intralevel dielectric.

9 . The electrical contact of claim 1 , wherein the third contact extends through an interlevel dielectric layer.

10 . The electrical contact of claim 1 , wherein the third contact portion has a base surface with a first width greater than the width of the second contact portion, and the third contact portion has an upper surface with a second width greater than the first width.

11 . A method of increasing the surface area of a contact to an electrical device comprising:
forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device; selectively forming a contact region of metal on an upper surface of the contact stud that is coplanar with an upper surface of the intralevel dielectric layer, wherein the selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the upper surface of the contact stud; and forming an interlevel dielectric layer on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

12 . The method of claim 11 , wherein the component of the electrical device comprises a field effect transistor, a metal oxide semiconductor field effect transistor, a fin field effect transistor, a memory device, a resistor, a capacitor or a combination thereof.

13 . The method of claim 11 , wherein said forming the contact stud comprises:
depositing the intralevel dielectric layer on the component of the electrical device; forming a via opening through the intralevel dielectric to a contact portion of the component; forming a metal liner on the sidewalls of the via opening; and filling the via opening with a conductive material for the first contact portion.

14 . The method of claim 11 , wherein said selectively forming the contact region on an upper surface of the contact stud that is coplanar with an upper surface of the intralevel dielectric layer comprises chemical vapor deposition or atomic layer deposition.

15 . A method of increasing the surface area of a contact to an electrical device comprising:
recessing an intralevel dielectric layer to expose sidewall surfaces of a contact stud that is extending through the intralevel dielectric layer to a component of the electrical device; selectively forming a contact region on a portion of the contact stud exposed by recessing said intralevel dielectric layer, wherein the selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud having said exposed sidewall surfaces; and forming an interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

16 . The method of claim 15 , wherein the component of the electrical device comprises a field effect transistor, a metal oxide semiconductor field effect transistor, a fin field effect transistor, a memory device, a resistor, a capacitor or a combination thereof.

17 . The method of claim 15 , wherein said forming the contact stud comprises:
depositing the intralevel dielectric layer on the component of the electrical device; forming a via opening through the intralevel dielectric to a contact portion of the component; forming a metal liner on the sidewalls of the via opening; and filling the via opening with a conductive material for the first contact portion.

18 . The method of claim 15 , wherein said selectively forming the contact region on an upper surface of the contact stud that is coplanar with an upper surface of the intralevel dielectric layer comprises atomic layer deposition or chemical vapor deposition.

19 . The method of claim 15 , wherein the contact stud comprises tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu) and combinations thereof.

20 . The method of claim 15 , wherein the selectively formed contact region comprises tungsten (W), cobalt (Co), ruthenium (Ru) or combinations thereof.

Assignees

• IBM

Inventors

• Clevenger Lawrence A
• Li Baozhen
• Peterson Kirk D
• Spooner Terry A
• Wang Junli

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10P14/432

  using selective deposition · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4432

  the principal metal being a noble metal, e.g. gold · CPC title

• H10W20/4421

  the principal metal being copper · CPC title