Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state

Patent metadata

Field	Value
Publication number	US-11847456-B2
Application number	US-202217961497-A
Country	US
Kind code	B2
Filing date	Oct 6, 2022
Priority date	Jun 20, 2016
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

First claim

What is claimed is:

1. A livelock recovery circuit for a processor having a program counter, wherein a value of the program counter is associated with a current instruction fetch and, for each of one or more previous instruction fetches, a value of the program counter is associated with that previous instruction fetch, the livelock recovery circuit comprising:
detection logic configured to:
store in memory, for each of the one or more previous instruction fetches, the value of the program counter associated with that previous instruction fetch,
determine the value of the program counter associated with the current instruction fetch, and
detect that the processor has illegally repeated an instruction by, for each value of the program counter stored in the memory, comparing the value of the program counter stored in the memory to the value of the program counter associated with the current instruction fetch to determine if the values are equal to detect repeated fetch of a same instruction; and

transition logic configured to, in response to the detection logic detecting that the processor has illegally repeated an instruction, cause the processor to transition to a known state.

2. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to detect that the processor has illegally repeated an instruction when the detection logic detects from the comparing (i) that a frequency of fetching a same instruction by the processor is greater than a threshold, or (ii) that the processor has fetched a same instruction more than a threshold number of times within a particular period.

3. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to detect that the processor has illegally repeated an instruction when the detection logic detects from the comparing that the processor has fetched an instruction from a same address two or more times within a predetermined number of consecutive instruction fetches.

4. The livelock recovery circuit of claim 3 , wherein the predetermined number of consecutive instruction fetches is an integer X, X is greater than one, and the one or more previous instruction fetches comprises X−1 instruction fetches preceding the current instruction fetch.

5. The livelock recovery circuit of claim 3 , wherein the processor is a single cycle non-pipelined processor and the predetermined number of consecutive instruction fetches is two.

6. The livelock recovery circuit of claim 5 , wherein the memory comprises a previous program counter vector configured to store the value of the program counter associated with a single previous instruction fetch.

7. The livelock recovery circuit of claim 3 , wherein the processor is a pipelined processor and the predetermined number of consecutive instruction fetches is greater than two.

8. The livelock recovery circuit of claim 7 , wherein the predetermined number of consecutive instruction fetches is an integer X, Xis greater than two, and the memory comprises a program counter buffer configured to store, for each instruction fetch of X−1 instruction fetches preceding the current instruction fetch, the value of the program counter associated with that instruction fetch.

9. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to detect that the processor has illegally repeated an instruction when the detection logic detects from the comparing that the processor has fetched an instruction from a same address more than a predetermined number of times between a start event and a stop event.

10. The livelock recovery circuit of claim 9 , wherein the start event is the processor being in an idle state and the stop event is the processor being in an idle state.

11. The livelock recovery circuit of claim 1 , wherein the detection logic comprises a livelock detected register and the detection logic is configured to, in response to detecting that the processor has illegally repeated an instruction, set the livelock detected register.

12. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to, in response to detecting that the processor has illegally repeated an instruction, generate a signal indicating that the detection logic has detected that the processor is in livelock.

13. The livelock recovery circuit of claim 1 , wherein the transition logic is configured to cause the processor to transition to the known state by setting a state of the processor to the known state.

14. The livelock recovery circuit of claim 13 , wherein the known state is an idle state.

15. The livelock recovery circuit of claim 1 , wherein the transition logic is configured to cause the processor to transition to the known state by invoking an interrupt.

16. The livelock recovery circuit of claim 1 , wherein the livelock recovery circuit is embodied in hardware on an integrated circuit.

17. A computer system comprising the livelock recovery circuit as set forth in claim 1 and said processor.

18. An integrated circuit manufacturing system comprising:
a computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes the livelock recovery circuit as set forth in claim 1 ;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of the integrated circuit embodying the livelock recovery circuit; and
an integrated circuit generation system configured to manufacture the livelock recovery circuit according to the circuit layout description.

19. A method of recovering a processor having a program counter from livelock, wherein a value of the program counter is associated with a current instruction fetch and, for each of one or more previous instruction fetches, a value of the program counter is associated with that previous instruction fetch, the method comprising:
storing, by a livelock recovery circuit, for each of the one or more previous instruction fetches, the value of the program counter associated with that previous instruction fetch in memory;
determining, by the livelock recovery circuit, the value of the program counter associated with the current instruction fetch;
detecting, by the livelock recovery circuit, that the processor has illegally repeated an instruction by, for each value of the program counter stored in the memory, comparing the value of the program counter stored in the memory to the value of the program counter associated with the current instruction fetch to determine if the values are equal to detect repeated fetch of a same instruction; and
in response to detecting that the processor has illegally repeated an instruction, causing, by the livelock recovery circuit, the processor to transition to a known state.

20. A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a livelock recovery circuit for a processor having a program counter, wherein a value of the program counter is associated with a current instruction fetch and, for each of one or more previous instruction fetches, a value of the program counter is associated with that previous instruction fetch, the livelock recovery circuit comprising:
detection logic configured to:
store in memory, for each of the one or more previous instruction fetches, the value

Assignees

• Imagination Tech Ltd

Inventors

• Darbari Ashish
• Singleton Iain

Classifications

• G06F9/325 Primary

  for loops, e.g. loop detection or loop counter · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3802

  Instruction prefetching · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3865

  using deferred exception handling, e.g. exception flags · CPC title