Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state

Patent metadata

Field	Value
Publication number	US-11467840-B2
Application number	US-202016743586-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Jun 20, 2016
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

First claim

What is claimed is:

1. A livelock recovery circuit for a processor comprising a program counter, the livelock recovery circuit comprising:
detection logic configured to monitor one or more control signals of the processor to detect if the processor illegally repeats an instruction; and
transition logic configured to, in response to the detection logic detecting that the processor has illegally repeated an instruction, cause the processor to transition to a known state;
wherein the detection logic is configured to detect that the processor has illegally repeated an instruction by, for each of one or more previous instruction fetches, comparing a value of the program counter associated with a current instruction fetch to a value of the program counter associated with one of the one or more previous instruction fetches to determine if the values are equal to detect repeated fetch of a same instruction.

2. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to detect that the processor has illegally repeated an instruction when the detection logic detects from the comparing (i) that a frequency of fetching a same instruction by the processor is greater than a threshold, or, (ii) that the processor has fetched a same instruction more than a threshold number of times within a particular period.

3. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to detect that the processor has illegally repeated an instruction when the detection logic detects from the comparing that the processor has fetched an instruction from a same address two or more times within a predetermined number of consecutive instruction fetches.

4. The livelock recovery circuit of claim 3 , wherein the predetermined number of consecutive instruction fetches is an integer X, where X is greater than one, and the one or more previous instruction fetches comprises X−1 instruction fetches preceding the current instruction fetch.

5. The livelock recovery circuit of claim 3 , wherein the processor is a single cycle non-pipelined processor and the predetermined number of consecutive instruction fetches is two.

6. The livelock recovery circuit of claim 5 , wherein the detection logic comprises a previous program counter vector to store a value of the program counter associated with a previous instruction fetch.

7. The livelock recovery circuit of claim 3 , wherein the processor is a pipelined processor and the predetermined number of consecutive instruction fetches is greater than two.

8. The livelock recovery circuit of claim 7 , wherein the predetermined number of consecutive instruction fetches is an integer X, where X is greater than two, and the detection logic comprises a program counter buffer to store the values of the program counter associated with a most recent X−1 instruction fetches.

9. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to detect that the processor has illegally repeated an instruction when the detection logic detects from the comparing that the processor has fetched an instruction from a same address more than a predetermined number of times between a start event and a stop event.

10. The livelock recovery circuit of claim 9 , wherein the start event is the processor being in an idle state and the stop event is the processor being in an idle state.

11. The livelock recovery circuit of claim 1 , wherein the detection logic comprises a livelock detected register and the detection logic is configured to set the livelock detected register upon detecting that the processor has illegally repeated an instruction.

12. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to, in response to detecting that the processor has illegally repeated an instruction, generate a signal indicating that the detection logic has detected the processor is in livelock.

13. The livelock recovery circuit of claim 1 , wherein the transition logic is configured to cause the processor to transition to the known state by setting a state of the processor to the known state.

14. The livelock recovery circuit of claim 13 , wherein the known state is an idle state.

15. The livelock recovery circuit of claim 1 , wherein the transition logic is configured to cause the processor to transition to the known state by invoking an interrupt.

16. The livelock recovery circuit of claim 1 , wherein the livelock recovery circuit is embodied in hardware on an integrated circuit.

17. A method of recovering a processor comprising a program counter from livelock, the method comprising:
monitoring, by a livelock recovery circuit, one or more control signals of the processor to detect when the processor has illegally repeated an instruction; and
in response to detecting that the processor has illegally repeated an instruction, causing, by the livelock recovery circuit, the processor to transition to a known state;
wherein detecting that the processor has illegally repeated an instruction comprises, for each of one or more previous instruction fetches, comparing a value of the program counter associated with a current instruction fetch to a value of the program counter associated with one of the one or more previous instruction fetches to determine if the values are equal to detect repeated fetch of a same instruction.

18. A computer system comprising the processor and the livelock recovery circuit as set forth in claim 1 .

19. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a livelock recovery circuit comprising:
detection logic configured to monitor one or more control signals of a processor comprising a program counter to detect if the processor illegally repeats an instruction; and
transition logic configured to, in response to the detection logic detecting that the processor has illegally repeated an instruction, cause the processor to transition to a known state;
wherein the detection logic is configured to detect that the processor has illegally repeated an instruction by, for each of one or more previous instruction fetches, comparing a value of the program counter associated with a current instruction fetch to a value of the program counter associated with one of the one or more previous instruction fetches to determine if the values are equal to detect repeated fetch of a same instruction.

Assignees

• Imagination Tech Ltd

Inventors

• Darbari Ashish
• Singleton Iain

Classifications

• G06F9/3802

  Instruction prefetching · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/3055

  Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16) · CPC title