Livelock recovery circuit configured to detect illegal repetition of an instruction and transition to a known state

Patent metadata

Field	Value
Publication number	US-10552155-B2
Application number	US-201615340554-A
Country	US
Kind code	B2
Filing date	Nov 1, 2016
Priority date	Jun 20, 2016
Publication date	Feb 4, 2020
Grant date	Feb 4, 2020

Abstract

Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.

First claim

The invention claimed is:

1. A livelock recovery circuit for a processor, the livelock recovery circuit comprising:
detection logic configured to monitor one or more control signals of the processor to detect if the processor illegally repeats an instruction; and
transition logic configured to, in response to the detection logic detecting that the processor has illegally repeated an instruction, cause the processor to transition to a known state;
wherein the detection logic is configured to detect that the processor has illegally repeated an instruction when the detection logic detects that the processor has fetched an instruction from a same address two or more times within a predetermined number of consecutive instruction fetches, or, when the detection logic detects that the processor has fetched an instruction from a same address more than a predetermined number of times between a start event and a stop event.

2. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to detect that the processor has illegally repeated an instruction when the detection logic detects (i) that a frequency of repetition of the instruction by the processor is greater than a threshold, or, (ii) that the processor has repeated the instruction more than a threshold number of times within a particular period.

3. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to detect that the processor has fetched an instruction from the same address two or more times within the predetermined number of consecutive instruction fetches by comparing a program counter value associated with a current instruction fetch with program counter values associated with the predetermined number of consecutive instruction fetches preceding the current instruction fetch.

4. The livelock recovery circuit of claim 1 , wherein the processor is a single cycle non-pipelined processor and the predetermined number of consecutive instruction fetches is one.

5. The livelock recovery circuit of claim 4 , wherein the detection logic comprises a previous program counter vector to store a program counter value associated with a previous instruction fetch.

6. The livelock recovery circuit of claim 1 , wherein the processor is a pipelined processor and the predetermined number of consecutive instruction fetches is greater than one.

7. The livelock recovery circuit of claim 6 , wherein the detection logic comprises a program counter buffer to store program counter values associated with a most recent predetermined number of instruction fetches.

8. The livelock recovery circuit of claim 1 , wherein the start event is the processor being in an idle state and the stop event is the processor being in an idle state.

9. The livelock recovery circuit of claim 1 , wherein the detection logic comprises a livelock detected register and the detection logic is configured to set the livelock detected register upon detecting that the processor has illegally repeated an instruction.

10. The livelock recovery circuit of claim 1 , wherein the detection logic is configured to, in response to detecting that the processor has illegally repeated an instruction, generate a signal indicating that the detection logic has detected the processor is in livelock.

11. The livelock recovery circuit of claim 1 , wherein the transition logic is configured to cause the processor to transition to the known state by setting a state of the processor to the known state.

12. The livelock recovery circuit of claim 11 , wherein the known state is an idle state.

13. The livelock recovery circuit of claim 1 , wherein the transition logic is configured to cause the processor to transition to the known state by invoking an interrupt.

14. The livelock recovery circuit of claim 1 , wherein the livelock recovery circuit is embodied on an integrated circuit.

15. A computer system comprising the livelock recovery circuit for a processor as set forth in claim 1 , and the processor.

16. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a livelock recovery circuit comprising:
detection logic configured to monitor one or more control signals of a processor to detect if the processor illegally repeats an instruction; and
transition logic configured to, in response to the detection logic detecting that the processor has illegally repeated an instruction, cause the processor to transition to a known state;
wherein detecting that the processor has illegally repeated an instruction comprises detecting that the processor has fetched an instruction from a same address two or more times within a predetermined number of consecutive fetches, or, detecting that the processor has fetched an instruction from a same address more than a predetermined number of times between a start event and a stop event.

17. A method of recovering a processor from livelock, the method comprising:
monitoring, by a livelock recovery circuit, one or more control signals of the processor to detect when the processor has illegally repeated an instruction; and
in response to detecting that the processor has illegally repeated an instruction, causing, by the livelock recovery circuit, the processor to transition to a known state;
wherein detecting that the processor has illegally repeated an instruction comprises, detecting, using the livelock recovery circuit, that the processor has fetched an instruction from a same address two or more times within a predetermined number of consecutive instruction fetches, or, detecting, using the livelock recovery circuit, that the processor has fetched an instruction from a same address more than a predetermined number of times between a start event and a stop event.

18. An integrated circuit manufacturing system comprising:
the non-transitory computer readable storage medium as set forth in claim 16 ;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of the integrated circuit embodying the livelock recovery circuit; and
an integrated circuit generation system configured to manufacture the livelock recovery circuit according to the circuit layout description.

Assignees

• Imagination Tech Ltd

Inventors

• Darbari Ashish
• Singleton Iain

Classifications

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title

• G06F9/3865

  using deferred exception handling, e.g. exception flags · CPC title

• G06F11/0721 Primary

  within a central processing unit [CPU] · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F11/0796

  Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element · CPC title