High voltage monolithic LED chip with improved reliability

Patent metadata

Field	Value
Publication number	US-11843083-B2
Application number	US-202318155556-A
Country	US
Kind code	B2
Filing date	Jan 17, 2023
Priority date	Jun 24, 2011
Publication date	Dec 12, 2023
Grant date	Dec 12, 2023

Abstract

Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another to minimize the visibility of the space during operation. The LED chips can also comprise layers structures and compositions that avow improved reliability under high current operation.

First claim

What is claimed is:

1. A monolithic LED chip, comprising:
an LED chip structure that is divided into a plurality of active regions;
electrically conductive interconnect elements between active regions of the plurality of active regions; and
first reflective elements that are arranged in passivation material, that are aligned with streets between adjacent active regions of the plurality of active regions, and that are electrically isolated from the plurality of active regions.

2. The monolithic LED chip of claim 1 , wherein the passivation material comprises SiO 2 .

3. The monolithic LED chip of claim 1 , wherein the passivation material comprises silicon nitride.

4. The monolithic LED chip of claim 1 , wherein a distance between adjacent active regions of the plurality of active regions is no more than 15 microns.

5. The monolithic LED chip of claim 1 , wherein a distance between adjacent active regions of the plurality of active regions is no more than 10 microns.

6. The monolithic LED chip of claim 1 , wherein a distance between adjacent active regions of the plurality of active regions is no more than 5 microns.

7. The monolithic LED chip of claim 1 , wherein a distance between adjacent active regions of the plurality of active regions is in a range from 0.05 microns to no more than 15 microns.

8. The monolithic LED chip of claim 1 , wherein the electrically conductive interconnect elements are in electrical contact with the plurality of active regions on a same side of the plurality of active regions.

9. The monolithic LED chip of claim 1 , wherein the first reflective elements comprise a higher reflectivity than a reflectivity of the electrically conductive interconnect elements.

10. The monolithic LED chip of claim 1 , wherein the electrically conductive interconnect elements comprise a material that resists electromigration under high current operation.

11. The monolithic LED chip of claim 1 , wherein the first reflective elements are arranged below said plurality of active regions, and arranged between the plurality of active regions and the electrically conductive interconnect elements.

12. The monolithic LED chip of claim 1 , further comprising second reflective elements that are arranged around an edge of one or more active regions of the plurality of active regions.

13. The monolithic LED chip of claim 12 , wherein the first and second reflective elements comprise discontinuous portions of at least one reflective layer.

14. The monolithic LED chip of claim 1 , wherein the plurality of active regions comprise a growth substrate.

15. The monolithic LED chip of claim 14 , wherein the growth substrate comprises sapphire.

16. The monolithic LED chip of claim 14 , wherein the growth substrate comprises silicon carbide.

Assignees

• Creeled Inc

Inventors

• Williams Bradley E
• Haberern Kevin W
• Langsdorf Bennett D
• Breva Manuel L

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/00

  Package configurations · CPC title