Semiconductor device

Patent metadata

Field	Value
Publication number	US-11843039-B2
Application number	US-202218074125-A
Country	US
Kind code	B2
Filing date	Dec 2, 2022
Priority date	Dec 14, 2020
Publication date	Dec 12, 2023
Grant date	Dec 12, 2023

Abstract

A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first gate insulating layer on the substrate;
second gate insulating layer arranged on the first gate insulating layer and including hafnium;
a gate electrode on the second gate insulating layer;
a gate capping pattern on the gate electrode;
a first gate spacer on a side surface of the gate electrode;
a second gate spacer on the first gate spacer;
a third gate spacer on the second gate spacer;
an interlayer insulating layer covering the third gate spacer; and
a contact plug in the interlayer insulating layer and electrically connected to the substrate,
wherein a width of the first gate insulating layer in a direction that is parallel to a top surface of the substrate is greater than a width of the second gate insulating layer in the direction,
the first gate spacer contacts a top surface of the first gate insulating layer and a side surface of the second gate insulating layer, and
the third gate spacer is spaced apart from the first gate insulating layer and the top surface of the substrate.

2. The semiconductor device of claim 1 , wherein the second gate spacer contacts a side surface of the first gate spacer and extends between the first gate insulating layer and the third gate spacer.

3. The semiconductor device of claim 1 , wherein the second gate spacer contacts a side surface of the first gate spacer and extends between the third gate spacer and the top surface of the substrate.

4. The semiconductor device of claim 1 , wherein a width of the second gate spacer in the direction is less than a width of one of the first gate spacer and the third gate spacer in the direction.

5. The semiconductor device of claim 1 , wherein the first gate spacer extends on a side surface of the gate capping pattern, and
a top surface of the first gate spacer is substantially coplanar with a top surface of the gate capping pattern.

6. The semiconductor device of claim 1 , wherein the second gate spacer contacts a side surface of the first gate spacer, a side surface of the first gate insulating layer, and the top surface of the substrate.

7. The semiconductor device of claim 1 , wherein the contact plug contacts a side surface of the third gate spacer.

8. The semiconductor device of claim 1 , wherein a dielectric constant of second gate insulating layer is greater than a dielectric constant of the first gate insulating layer.

9. The semiconductor device of claim 1 , wherein each of the first gate spacer and the third gate spacer include nitrogen and the second gate spacer includes oxygen.

10. The semiconductor device of claim 1 , wherein a bottom surface of the first gate spacer is higher than a bottom surface of the second gate spacer.

11. A semiconductor device comprising:
a substrate;
a first gate insulating layer on the substrate;
a second gate insulating layer arranged on the first gate insulating layer and including hafnium and aluminum;
a gate electrode on the second gate insulating layer;
a gate capping pattern on the gate electrode;
a first gate spacer on a side surface of the gate electrode;
a second gate spacer on the first gate spacer;
a third gate spacer on the second gate spacer;
an interlayer insulating layer covering the third gate spacer; and
a contact plug in the interlayer insulating layer and electrically connected to the substrate,
wherein a width of the second gate spacer in a direction that is parallel to a top surface of the substrate is less than a width of one of the first gate spacer and the third gate spacer in the direction,
the second gate spacer contacts a side surface of the first gate spacer and extends on the top surface of the substrate,
the third gate spacer is spaced apart from the top surface of the substrate, and
a width of the first gate insulating layer in the direction is greater than a width of the second gate insulating layer in the direction.

12. The semiconductor device of claim 11 , wherein the second gate spacer is between the first gate insulating layer and the third gate spacer, and is between the third gate spacer and the top surface of the substrate.

13. The semiconductor device of claim 11 , wherein the first gate spacer contacts a top surface of the first gate insulating layer and a side surface of the second gate insulating layer.

14. The semiconductor device of claim 11 , wherein the first gate spacer extends on a side surface of the gate capping pattern, and
a top surface of the first gate spacer is substantially coplanar with a top surface of the gate capping pattern.

15. The semiconductor device of claim 11 , wherein the gate electrode includes titanium nitride, doped poly-silicon, and tungsten.

16. The semiconductor device of claim 11 , wherein the contact plug contacts a side surface of the third gate spacer.

17. The semiconductor device of claim 11 , wherein a dielectric constant of second gate insulating layer is greater than a dielectric constant of the first gate insulating layer.

18. The semiconductor device of claim 11 , wherein each of the first gate spacer and the third gate spacer include nitrogen and the second gate spacer includes oxygen.

19. The semiconductor device of claim 11 , wherein a bottom surface of the first gate spacer is higher than a bottom surface of the second gate spacer.

20. A semiconductor device comprising:
a substrate;
a first gate insulating layer on the substrate;
a second gate insulating layer arranged on the first gate insulating layer and including hafnium and aluminum;
a gate electrode on the second gate insulating layer;
a gate capping pattern on the gate electrode;
a first gate spacer on a side surface of the gate electrode;
a second gate spacer on the first gate spacer;
a third gate spacer on the second gate spacer;
an interlayer insulating layer covering the third gate spacer; and
a contact plug in the interlayer insulating layer and electrically connected to the substrate,
wherein a width of the second gate spacer in a direction that is parallel to a top surface of the substrate is less than a width of one of the first gate spacer and the third gate spacer in the direction,
the second gate spacer contacts a side surface of the first gate spacer and extends on the top surface of the substrate,
the third gate spacer is spaced apart from the top surface of the substrate, and
the first gate spacer contacts a top surface of the first gate insulating layer and a side surface of the second gate insulating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Back Doosan
• Kim Dongoh
• Kil Gyuhyun
• Han Jung-Hoon

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D84/0144 Primary

  Manufacturing their gate insulating layers · CPC title

• H10D84/0147 Primary

  Manufacturing their gate sidewall spacers · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/251

  Source or drain electrodes for field-effect devices · CPC title