Hard mask for patterning magnetic tunnel junctions
US-2016351799-A1 · Dec 1, 2016 · US
US11839162B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11839162-B2 |
| Application number | US-202117358990-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 25, 2021 |
| Priority date | Nov 22, 2019 |
| Publication date | Dec 5, 2023 |
| Grant date | Dec 5, 2023 |
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Magnetoelectric or magnetoresistive memory cells may include a plurality of reference layers and optionally a plurality of free layers to enhance the tunneling magnetoresistance (TMR) ratio.
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What is claimed is: 1. A memory device, comprising: a first electrode; a second electrode; a magnetic tunnel junction located between the first electrode and the second electrode and comprising: a plurality of reference layers spaced apart from each other; at least one free layer; and a first nonmagnetic tunnel barrier layer interposed between a most proximal one of the plurality of reference layers and the at least one free layer; and a composite synthetic antiferromagnet (SAF) structure located between the first electrode and the magnetic tunnel junction, wherein the SAF structure comprises a first superlattice, a second superlattice, and an antiferromagnetic coupling layer located between the first superlattice and the second superlattice; wherein: the antiferromagnetic coupling layer comprises an iridium layer; the first superlattice comprises the first superlattice of first cobalt layers and first platinum layers; and the second superlattice comprises the second superlattice of second cobalt layers and second platinum layers. 2. The memory device of claim 1 , wherein: the first superlattice comprises N1 repetitions of a first unit layer stack of the first cobalt layer and the first platinum layer, and a first capping cobalt layer, such that N1 of the first platinum layers are interlaced with (N1+1) of the first cobalt layers; N1 is an integer in a range from 2 to 10; the second superlattice comprises N2 repetitions of a second unit layer stack of the second cobalt layer and the second platinum layer, and a second capping cobalt layer, such that N2 first platinum layers are interlaced with (N2+1) second cobalt layers; and N2 is an integer in a range from 2 to 10. 3. The memory device of claim 2 , further comprising a tungsten layer located between the SAF structure and the magnetic tunnel junction. 4. The memory device of claim 3 , further comprising a tantalum seed layer and a platinum seed layer located between the first electrode and the SAF structure. 5. The memory device of claim 4 , wherein: the tantalum seed layer and the platinum seed layer are located over the first electrode; the SAF structure is located over the tantalum seed layer and the platinum seed layer; the tungsten layer is located over the SAF structure; a first reference layer of the plurality of reference layers is located over the tungsten layer; a second reference layer of the plurality of reference layers is located over the first reference layer; the first nonmagnetic tunnel barrier layer is located over the second reference layer; and the at least one free layer is located over the first nonmagnetic tunnel barrier layer. 6. A memory device, comprising: a first electrode; a second electrode; a magnetic tunnel junction located between the first electrode and the second electrode and comprising at least one reference layer, at least one free layer, and a nonmagnetic tunnel barrier layer interposed between the at least one reference layer and the at least one free layer; and a composite synthetic antiferromagnet (SAF) structure located between the first electrode and the magnetic tunnel junction, wherein: the SAF structure comprises a first superlattice, a second superlattice, and an antiferromagnetic coupling layer located between the first superlattice and the second superlattice; the first superlattice comprises N1 repetitions of a first unit layer stack of a first cobalt layer and a first platinum layer, and a first capping cobalt layer, such that N1 of the first platinum layers are interlaced with (N1+1) of the first cobalt layers; N1 is an integer in a range from 2 to 10; the second superlattice comprises N2 repetitions of a second unit layer stack of a second cobalt layer and a second platinum layer, and a second capping cobalt layer, such that N2 first platinum layers are interlaced with (N2+1) second cobalt layers; and N2 is an integer in a range from 2 to 10. 7. The memory device of claim 6 , further comprising: a tungsten layer located between the SAF structure and the magnetic tunnel junction; and a tantalum seed layer and a platinum seed layer located between the first electrode and the SAF structure. 8. The memory device of claim 7 , wherein: the antiferromagnetic coupling layer comprises an iridium layer; the tantalum seed layer and the platinum seed layer are located over the first electrode; the SAF structure is located over the tantalum seed layer and the platinum seed layer; the tungsten layer is located over the SAF structure; the at least one reference layer is located over the tungsten layer; the nonmagnetic tunnel barrier layer is located over the at least one reference layer; and the at least one free layer is located over the nonmagnetic tunnel barrier layer. 9. The memory device of claim 8 , wherein the at least one reference layer comprises a first reference layer and a second reference layer which are spaced apart from each other.
Constructional details · CPC title
details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title
Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect · CPC title
the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title
Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy · CPC title
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