Comparator, ad converter, photoelectric conversion device, imaging system, and movable object

Patent metadata

Field	Value
Publication number	US-11838665-B2
Application number	US-202117176395-A
Country	US
Kind code	B2
Filing date	Feb 16, 2021
Priority date	Feb 26, 2020
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A disclosed comparator includes a comparison circuit that performs comparison between an input signal and a reference signal and changes a level of a signal to be output to a first node in accordance with a result of the comparison; and a positive feedback circuit including an amplifier unit that includes a current source load and outputs a signal in accordance with a potential of the first node to a second node and a feedback unit that positively feeds back a signal in accordance with a potential of the second node to the first node. The feedback unit includes a first transistor to which output of the amplifier unit is fed back and a switch that controls turning on or off of the first transistor.

First claim

What is claimed is:

1. A comparator comprising:
a comparison circuit that performs comparison between an input signal and a reference signal and changes a level of a signal to be output to a first node in accordance with a result of the comparison; and
a positive feedback circuit including an amplifier unit that includes a current source load and outputs a signal in accordance with a potential of the first node to a second node, and a feedback unit that positively feeds back a signal in accordance with a potential of the second node to the first node,
wherein the feedback unit includes a first transistor to which output of the amplifier unit is fed back and a switch that controls turning on or off of the first transistor, and
wherein the amplifier unit of the positive feedback circuit includes a second transistor of a first conductivity type whose first main node is connected to a first voltage node supplied with a first voltage and whose control node is connected to the first node and a first current source load connected between a second voltage node supplied with a second voltage, which is different from the first voltage, and a second main node of the second transistor.

2. The comparator according to claim 1 ,
wherein the comparison circuit includes a differential unit to which the input signal and the reference signal are input, and an amplifier unit connected to an output node of the differential unit, and
wherein the amplifier unit of the comparison circuit includes a third transistor of the first conductivity type whose first main node is connected to a third voltage node supplied with the first voltage, whose second main node is connected to the first node, and whose control node is connected to the output node of the differential unit.

3. The comparator according to claim 1 , wherein the amplifier unit of the positive feedback circuit further includes a fourth transistor of the first conductivity type whose first main node is connected to the first voltage node and whose control node is connected to the first node and a third current source load connected between a second main node of the fourth transistor and the second voltage node.

4. The comparator according to claim 1 , wherein the amplifier unit of the positive feedback circuit further includes a seventh transistor of a second conductivity type whose first main node is connected to the first voltage node and whose control node is connected to the first node and a fourth current source load connected between a second main node of the seventh transistor and the second voltage node.

5. The comparator according to claim 1 further comprising a reset switch connected between a fourth node supplied with the second voltage and the first node.

6. The comparator according to claim 1 ,
wherein the switch is an eighth transistor of the first conductivity type whose first main node is connected to a fifth voltage node supplied with the first voltage, and
wherein the first transistor is of the first conductivity type and has a first main node connected to a second main node of the eighth transistor, a second main node connected to the first node, and a control node connected to the second main node of the second transistor.

7. The comparator according to claim 1 ,
wherein the switch is a ninth transistor of a second conductivity type whose first main node is connected to the first node, and
wherein the first transistor is of the second conductivity type and has a first main node connected to a second main node of the ninth transistor, a second main node connected to a sixth voltage node supplied with the second voltage, and a control node connected to the second main node of the second transistor.

8. The comparator according to claim 1 , wherein the first voltage is a power supply voltage, and the second voltage is a reference voltage.

9. The comparator according to claim 1 , wherein the current source load forms a gate grounded circuit and includes a tenth transistor whose control node is supplied with a bias voltage that is different from a reference voltage and a bias hold capacitor connected to a control node of the tenth transistor.

10. The comparator according to claim 1 , wherein the second node is an output node of the positive feedback circuit.

11. The comparator according to claim 1 , wherein the first node is an output node of the positive feedback circuit.

12. The comparator according to claim 1 , wherein the comparison circuit includes a clamp capacitor provided to a node to which the input signal is input and a clamp capacitor provided to a node to which the reference signal is input.

13. A photoelectric conversion device comprising:
a plurality of pixel units arranged so as to form a plurality of rows and a plurality of columns and each including a pixel including a photoelectric converter and the comparator according to claim 1 in which a signal in accordance with charge generated in the photoelectric converter of the pixel is the input signal;
a plurality of output lines arranged on each of the plurality of columns and each connected to the pixel units on a corresponding column; and
a counter circuit that is provided in association with each of the plurality of output lines and outputs, as digital data of the input signal, a count value in accordance with a length of a period from start of comparison between the input signal and the reference signal to a change of a level of a signal output from the pixel unit on a corresponding column.

14. The comparator according to claim 2 , wherein the amplifier unit of the comparison circuit further includes a second current source load connected between a fourth voltage node supplied with the second voltage and the second main node of the third transistor.

15. The comparator according to claim 14 , wherein the first current source load and the second current source load are configured to cancel respective current fluctuations.

16. The comparator according to claim 14 ,
wherein the comparison circuit is configured to output a high-level signal or a low-level signal, and
wherein a current amount of the second current source load is less than a current amount of the first current source load when an output of the comparison circuit is one of the high-level signal and the low-level signal, and the current amount of the second current source load is greater than the current amount of the first current source load when the output of the comparison circuit is the other of the high-level signal and the low-level signal.

17. The comparator according to claim 3 , wherein the amplifier unit of the positive feedback circuit further includes a fifth transistor of the first conductivity type connected between the first main node of the second transistor and the first voltage node and a sixth transistor of the first conductivity type connected between the first main node of the fourth transistor and the first voltage node.

18. The comparator according to claim 6 further comprising:
a pad electrode used for supplying the first voltage;
a first interconnection connected between the pad electrode and at least one of the first voltage node and the fifth voltage node; and
a second interconnection connected between the pad electrode and the comparison circuit.

19. The comparator according to claim 6 further comprising:
a first pad electrode and a second pad electrode used for supplying the first voltage;
a first interconnection connected between the first pad electrode and at least one of the first voltage node and the fifth vo

Assignees

• Canon Kk

Inventors

• Kobayashi Hideo
• Hasegawa So

Classifications

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• H04N25/75 Primary

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title

• H03M1/0607

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title