Readout circuit, solid-state imaging apparatus, and method for driving readout circuit

Patent metadata

Field	Value
Publication number	US-9270905-B2
Application number	US-201313919810-A
Country	US
Kind code	B2
Filing date	Jun 17, 2013
Priority date	Jul 12, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A readout circuit includes: an amplifier ( 408 ); and offset controllers ( 415 and 416 ) configured to set an output offset voltage of the amplifier, wherein the readout circuit operates in first and second modes, in the first mode, a first voltage, and thereafter a second voltage lower than the first voltage, are input into the amplifier, in the second mode, a third voltage, and thereafter a fourth voltage higher than the third voltage, are input into the amplifier, and the offset controller switches the output offset voltage of the amplifier, between the first and second modes.

First claim

What is claimed is:

1. A readout circuit comprising:
an amplifier;
an input capacitor configured to input a signal by capacitive coupling to an input terminal of the amplifier;
an initializing switch configured to short circuit between the input terminal and an output terminal of the amplifier;
a feedback capacitor arranged between the input terminal and the output terminal of the amplifier; and
an offset controller configured to set an output offset voltage of the amplifier, wherein
the readout circuit operates in first and second modes,
in the first mode, a first voltage is input to the amplifier through the input capacitor, and thereafter a second voltage lower than the first voltage is input to the amplifier through the input capacitor,
in the second mode, a third voltage is input to the amplifier through the input capacitor, and thereafter a fourth voltage higher than the third voltage is input to the amplifier through the input capacitor, and
in at least one of the first mode and the second mode, after the initializing switch is turned on, the offset controller applies the output offset voltage to the output terminal of the amplifier, whereby the output offset voltage of the amplifier is set to different values between the first and second modes.

2. The readout circuit according to claim 1 , wherein
the input capacitor, the initializing switch and the feedback capacitor constitute a clamping unit configured to clamp the first voltage in the first mode, and to clamp the third voltage in the second mode.

3. The readout circuit according to claim 1 , wherein
the amplifier is a differential amplifier or a common source type amplifier.

4. The readout circuit according to claim 1 , wherein
in the first mode, after the initializing switch is turned on, the first voltage is input to the input capacitor to clamp the first voltage, and
in the second mode, after the initializing switch is turned on, the third voltage is input to the input capacitor to clamp the third voltage.

5. The readout circuit according to claim 1 , wherein
the offset controller controls so that a transition period of a control signal for switching from on to off of the initializing switch in the first mode is different from a transition period of the control signal for switching from on to off of the initializing switch in the second mode, whereby the output offset voltage of the amplifier is set to the different values between the first and second modes.

6. The readout circuit according to claim 1 , wherein
the amplifier is a differential amplifier, and
a reference voltage input to the differential amplifier in the first mode is different from a reference voltage input to the differential amplifier in the second mode.

7. The readout circuit according to claim 1 , wherein
a plurality of the initializing switches are provided, and
the offset controller controls so that a number of the initializing switches turned on in the first mode is different from a number of the initializing switches turned on in the second mode, whereby the output offset voltage of the amplifier is set to the different values between the first and second modes.

8. The readout circuit according to claim 1 , wherein
the offset controller applies different offset voltages to a node on an electrical path between the feedback capacitor and the output terminal of the amplifier in an on state of the initializing switch in the first mode and in an on state of the initializing switch in the second mode, whereby the output offset voltage of the amplifier is set to the different values between the first and second modes.

9. The readout circuit according to claim 1 , further comprising a second capacitor including a first terminal connected to the input terminal of the amplifier and a second terminal connected to the offset controller, wherein
the offset controller applies different voltages to the second terminal of the second capacitor between the first and second modes, whereby the output offset voltage of the amplifier is set to different values between the first and second modes.

10. The solid-state imaging device according to claim 9 , wherein
in the first mode, a photo signal from the pixel is input to the first input terminal as the first voltage, and a pixel reset signal from the pixel is input to the first input terminal as the second voltage, and
in the second mode, a pixel reset signal from the pixel is input to the first input terminal as the third voltage, and a photo signal from the pixel is input to the first input terminal as the fourth voltage.

11. A solid-state imaging apparatus comprising:
a readout circuit including:
an amplifier;
an input capacitor configured to input a signal by capacitive coupling to an input terminal of the amplifier;
an initializing switch configured to short circuit between the input terminal and an output terminal of the amplifier;
a feedback capacitor arranged between the input terminal and the output terminal of the amplifier; and
an offset controller configured to set an output offset voltage of the amplifier, wherein
the readout circuit operates in first and second modes,
in the first mode, a first voltage is input to the amplifier through the input capacitor, and thereafter a second voltage lower than the first voltage is input to the amplifier through the input capacitor,
in the second mode, a third voltage is input to the amplifier through the input capacitor, and thereafter a fourth voltage higher than the third voltage is input to the amplifier through the input capacitor, and
in at least one of the first mode and the second mode, after the initializing switch is turned on, the offset controller applies the output offset voltage to the output terminal of the amplifier, whereby the output offset voltage of the amplifier is set to different values between the first and second modes; and
a pixel configured to generate a signal by a photoelectric conversion, wherein
the signal generated by the pixel is input to the readout circuit.

12. The solid-state imaging apparatus according to claim 11 , further comprising:
an output amplifier configured
to output, in the first mode, a difference between an output voltage from the amplifier at a time of inputting the first voltage and an output voltage from the amplifier at a time of inputting the second voltage, and
to output, in the second mode, a difference between an output voltage from the amplifier at a time of inputting the third voltage and an output voltage from the amplifier at a time of inputting the fourth voltage.

13. A method of driving a readout circuit comprising an amplifier, an input capacitor configured to input a signal by capacitive coupling to an input terminal of the amplifier, an initializing switch configured to short circuit between the input terminal and an output terminal of the amplifier, a feedback capacitor arranged between the input terminal and the output terminal of the amplifier, and an offset controller configured to set an output offset voltage of the amplifier; wherein the method comprises:
operating the readout circuit in first and second modes;
in the first mode, inputting, to the amplifier through the input capacitor, a first voltage, and thereafter inputting a second voltage lower than the first voltage through the input capacitor;
in the second mode, inputting, to the amplifier through the input capacitor, a third voltage, and thereafter inputting a fourth voltage higher than the third voltage through the input capacitor, and
in at least one of the first mode and the second mode, after turning on the initializing switch, applying the output

Assignees

• Canon Kk

Inventors

• Ogura Masanori
• Kobayashi Hideo
• Kochi Tetsunobu

Classifications

• H04N25/00 Primary

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N23/667

  Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H03F2203/45101

  Control of the DC level being present · CPC title

• H04N5/23245

  Electricity · mapped topic