Electronic circuit and camera

Patent metadata

Field	Value
Publication number	US-9947615-B2
Application number	US-201615044628-A
Country	US
Kind code	B2
Filing date	Feb 16, 2016
Priority date	Feb 27, 2015
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

An electronic circuit includes a generating circuit for generating a first group of signals and a second group of signals, and a transmission path for transmitting the first group of signals and the second group of signals. The first group of signals are composed of signals synchronized with a first edge that is one of the rising edge and the falling edge of a reference clock, and the second group of signals are composed of signals synchronized with a second edge that is the other of the rising edge and falling edge. The transmission path includes first transmission lines for transmitting the signals composing the first group and second transmission lines for transmitting the signals composing the second group, and the first and second transmission lines are alternately arranged.

First claim

What is claimed is:

1. An electronic circuit comprising:
a generating circuit having a first output node and a second output node, the first output node configured to output a first signal, the second output node configured to output a second signal, the second signal having a cycle shorter than a cycle of the first signal
a first decoder having a first input node and a third output node;
a second decoder having a second input node, a third input node and a fourth output node; and
a transmission path including a first transmission line and a second transmission line, the first transmission line being electrically connected to the first output node, the second transmission line being electrically connected to the second output node
wherein the first signal is synchronized with a first edge that is one of the rising edge and the falling edge of a reference clock, and the second signal is synchronized with a second edge that is the other of the rising edge and falling edge of the reference clock,
the first input node is electrically connected to the first transmission line,
the third output node is configured to control a signal input to the second input node,
the third input node is electrically connected to the second transmission line, and
the second decoder outputs a decoded signal generated in accordance with signals input to the second input node and the third input node.

2. A camera comprising:
a solid state image sensor including the electronic circuit according to claim 1 ; and
a processor configured to process a signal output from the solid state image sensor.

3. The electronic circuit according to claim 1 ,
wherein the generating circuit generates a first group of signals including the first signal, and a second group of signals including the second signal,
wherein the first group of signals are synchronized with the first edge, and the second group of signals are synchronized with the second edge,
wherein the transmission path includes a plurality of first transmission lines including the first transmission line, each configured to transmit corresponding one of the first group of signals and a plurality of second transmission lines including the second transmission line, each configured to transmit corresponding one of the second group of signals, and
wherein the plurality of first transmission lines and the plurality of second transmission lines are alternately arranged.

4. The electronic circuit according to claim 3 , wherein the generating circuit includes a logic circuit configured to generate a plurality of bit signals by operating in response to the reference clock and a timing adjusting circuit configured to generate the first group of signals and the second group of signals in accordance with the plurality of bit signals output from the logic circuit.

5. The electronic circuit according to claim 4 , wherein the timing adjusting circuit includes a plurality of first flip flops configured to generate the first group of signals by performing synchronization in accordance with the first edge and a plurality of second flip flops configured to generate the second group of signals by performing synchronization in accordance with the second edge, and
a signal line configured to provide the first edge to the plurality of first flip flops and a signal line configured to provide the second edge to the plurality of second flip flops do not intersect with each other.

6. The electronic circuit according to claim 5 , wherein the logic circuit includes a counter configured to perform a count operation in response to the reference clock.

7. The electronic circuit according to claim 6 , further comprising:
a pixel array that includes a plurality of pixels, and
an A/D converter configured to A/D-convert a signal from the pixel array,
wherein the count value from the counter is supplied to the A/D converter.

8. The electronic circuit according to claim 6 , further comprising:
a pixel array that includes a plurality of pixels arranged in rows and columns, and
a selecting circuit configured to select a row of the rows,
wherein the selecting circuit includes the first decoder and the second decoder.

9. The electronic circuit according to claim 4 , wherein the logic circuit includes a counter configured to perform a count operation in response to the reference clock.

10. The electronic circuit according to claim 9 , wherein the counter comprises a binary counter.

11. The electronic circuit according to claim 9 , wherein the counter comprises a Gray code counter.

12. The electronic circuit according to claim 11 , wherein the counter has at least one of a function to reset a count value and a function to set a count value.

13. The electronic circuit according to claim 9 , further comprising:
a pixel array that includes a plurality of pixels, and
an A/D converter configured to A/D-convert a signal from the pixel array,
wherein the count value from the counter is supplied to the A/D converter.

14. The electronic circuit according to claim 9 , further comprising:
a pixel array that includes a plurality of pixels arranged in rows and columns, and
a selecting circuit configured to select a row of the rows,
wherein the selecting circuit includes the first decoder and the second decoder.

15. The electronic circuit according to claim 3 , further comprising:
a synchronizing circuit configured to perform synchronization so that the first group of signals and the second group of signals transmitted via the transmission path are synchronized with only one of the first edge and the second edge.

16. The electronic circuit according to claim 1 , wherein the third output node is connected to the second input node via a synchronization circuit.

17. The electronic circuit according to claim 16 , wherein the synchronization circuit outputs, to the second input node, a signal generated by synchronizing a signal output from the third output node with a clock signal.

Assignees

• Canon Kk

Inventors

• Kobayashi Hideo
• Yamazaki Kazuo
• Hiyama Hiroki

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H04N25/745 Primary

  Circuitry for generating timing or clock signals · CPC title

• H04N25/70 Primary

  SSIS architectures; Circuits associated therewith · CPC title

• H01L23/58

  Electricity · mapped topic