Inverter

Patent metadata

Field	Value
Publication number	US-11837523-B2
Application number	US-202217966614-A
Country	US
Kind code	B2
Filing date	Oct 14, 2022
Priority date	Oct 25, 2016
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

First claim

What is claimed is:

1. A method for producing a transistor package, the method comprising:
providing a substrate;
depositing a first transistor such that the first transistor is in thermal contact with the substrate;
directly sintering the substrate to a heat sink through a sintering layer;
at least partially encapsulating the first transistor with an encapsulant; and
creating a Kelvin connection to the first transistor, the Kelvin connection having a first connector directly coupled at a first end to a transistor gate of the first transistor and a second connector directly coupled at a first end to a differing terminal of the first transistor, wherein the encapsulant further encapsulates a portion of each of the first connector and the second connector, including the first end of the first connector and the first end of the second connector.

2. The method of claim 1 , wherein the heat sink comprises fins and contact pads.

3. The method of claim 1 , further comprising providing a second transistor that is in series with the first transistor.

4. The method of claim 3 , wherein the first transistor is an insulated-gate bipolar transistor and the second transistor is a diode transistor.

5. The method of claim 3 , wherein the first transistor is a metal-oxide-semiconductor-field-effect transistor and the second transistor is a diode transistor.

6. The method of claim 1 , wherein the transistor package further comprises a copper cladding layer and the Kelvin connection is further connected to a busbar.

7. The method of claim 1 , wherein the first transistor comprises a gallium nitride or a silicon carbide wideband semiconductor.

8. The method of claim 1 , wherein the sintering includes applying a first force from above the encapsulated first transistor and applying a second force from below the heatsink in a direction opposite to the first force.

9. The method of claim 8 , wherein the first force is applied utilizing a first independently actuated press block.

10. The method of claim 8 , wherein the second force is applied utilizing a second independently actuated press block.

11. The method of claim 10 , wherein the second independently actuated press block is double sided.

12. The method of claim 1 , additionally comprising providing an external busbar connector, the connector having a “U”-bend shape being connected to the transistor package.

13. The method of claim 1 , additionally comprising providing a busbar connector interconnecting the first transistor to either a positive busbar or a negative busbar for providing current to the first transistor.

14. A method for producing a transistor package, the method comprising:
providing a cladding layer;
depositing a first transistor such that the first transistor is in thermal contact with the cladding layer;
directly sintering the cladding layer to a heat sink through a sintering layer;
at least partially encapsulating the first transistor with an encapsulant; and
creating a Kelvin connection to the first transistor, the Kelvin connection having a first connector directly coupled at a first end to a transistor gate of the first transistor and a second connector directly coupled at a first end to a differing terminal of the first transistor, wherein the encapsulant further encapsulates a portion of each of the first connector and the second connector, including the first end of the first connector and the first end of the second connector.

15. The method of claim 14 , wherein the cladding layer comprises copper.

16. The method of claim 14 , further comprising providing a second transistor that is in series with the first transistor.

17. The method of claim 16 , wherein the first transistor is an insulated-gate bipolar transistor or a metal-oxide-semiconductor-field-effect transistor and the second transistor is a diode transistor.

18. The method of claim 14 , wherein the sintering includes applying a first force from above the encapsulated first transistor and applying a second force from below the heatsink in a direction opposite to the first force.

19. The method of claim 18 , wherein the first force is applied utilizing a first independently actuated press block and the second force is applied utilizing a second independently actuated press block.

20. The method of claim 14 , additionally comprising providing an external busbar connector, the connector having a “U”-bend shape being connected to the transistor package.

21. A method for producing a transistor package, the method comprising:
providing a substrate;
depositing an insulated-gate bipolar transistor such that the transistor is in thermal contact with the substrate;
directly sintering the substrate to a heat sink through a sintering layer;
at least partially encapsulating the insulated-gate bipolar transistor with an encapsulant; and
creating a Kelvin connection to the insulated-gate bipolar transistor, the Kelvin connection having a first connector directly coupled at a first end to a gate of the insulated-gate bipolar transistor and a second connector directly coupled at a first end to an emitter of the insulated-gate bipolar transistor, wherein the encapsulant further encapsulates a portion of each of the first connector and the second connector, including the first end of the first connector and the first end of the second connector.

22. The method of claim 21 , further comprising providing another transistor that is in series with the insulated-gate bipolar transistor.

Assignees

• Tesla Inc

Inventors

• Liu Wenjun
• Ramm Robert James
• Tepe Alan David
• Campbell Colin Kenneth
• Sasaridis Dino

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/07141

  Means for applying energy, e.g. ovens or lasers · CPC title