Signal pin arrangement for multi-device power module

Patent metadata

Field	Value
Publication number	US-10137789-B2
Application number	US-201615214630-A
Country	US
Kind code	B2
Filing date	Jul 20, 2016
Priority date	Jul 20, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A power module provides one or more power transistors and support elements in a card shape. The pins/terminals for signal-level input/outputs (e.g., gate drive, current sensor, and temperature sensor signals) are arranged in two parallel layers. The power terminals (e.g., positive and negative bus, and output junction of a phase leg) are preferably arranged in just one of the layers. The signal pins are spaced both laterally across a long edge of the power module and transversely to the edge direction, so that the minimum spacings (i.e., clearances) can be achieved while shortening the lateral length of the edge(s) of the power module. Preferably, the signal pins belonging to an individual power transistor (e.g., an IGBT or MOSFET) are distributed between the two layers so that corresponding signal loops can be magnetically decoupled from the power terminal loop.

First claim

What is claimed is:

1. A power module comprising:
a first insulating substrate having a bonded copper layer on a first side defining circuit traces, a plurality of first signal pins, and a plurality of power terminals, wherein the first signal pins and power terminal are coplanar and each cantilevers beyond an edge of the first substrate;
at least one semiconductor chip containing a power transistor and having a side soldered to a respective circuit trace on the first substrate that extends to one of the power terminals;
a second insulating substrate parallel to the first substrate and having a bonded copper layer on an interior side facing the first side and defining circuit traces and a plurality of second signal pins, wherein the second signal pins are coplanar and each cantilevers beyond an edge of the second substrate, wherein the chip includes a plurality of signal pads, wherein a first group of the signal pads are each connected to a respective first signal pin, and wherein a second group of the signal pads are each connected to a respective second signal pin;
a plurality of spacers each soldered between the first side and the interior side; and
an encapsulating body securing the substrates, chip, and spacers, wherein the signal pins and power terminals extend through the encapsulating body.

2. The module of claim 1 comprising a plurality of semiconductor chips soldered to respective circuit traces on the first and second substrates, wherein each chip contains a respective power transistor, and wherein power terminals for all the power transistors all extend from the first substrate.

3. The module of claim 1 wherein a pair of the signal pads are adapted to receive a gate drive signal for the power transistor, wherein the first group includes one of the pair of gate drive signal pads and the second group includes the other of the pair of gate drive signal pads.

4. The module of claim 3 wherein respective first and second signal pins connected to the pair of gate drive signal pads are transversely aligned with respect to the edge of the first substrate, whereby a magnetic field associated with a gate current in the first and second signal pins is oriented transverse to a magnetic field associated with a switched current in the power terminals.

5. The module of claim 1 wherein a pair of the signal pads are adapted to provide a chip temperature signal, wherein the first group includes one of the pair of temperature signal pads and the second group includes the other of the pair of temperature signal pads.

6. The module of claim 5 wherein respective first and second signal pins connected to the pair of temperature signal pads are transversely aligned with respect to the edge of the first substrate, whereby a magnetic field associated with a temperature signal in the first and second signal pins is oriented transverse to a magnetic field associated with a switched current in the power terminals.

7. The module of claim 1 wherein the first signal pins and the power terminals extend from opposite edges of the first substrate.

8. The module of claim 7 wherein the first and second signal pins extend from proximate edges of the first and second substrates, respectively.

9. The module of claim 1 wherein the first and second substrates each has an exterior side comprised of a bonder copper layer adapted to transfer heat generated in the power transistor.

10. A power module comprising:
a pair of spaced apart substrates having circuit traces connecting a plurality of signal pins and power terminals respectively thereon and coplanarly cantilevered beyond edges of the substrates;
at least one semiconductor chip attached to a circuit trace on one of the substrates;
a plurality of spacers between the substrates; and
an encapsulating body;
wherein spacing of paired signal pins and spacing of paired power terminals are transverse for magnetic decoupling.

11. The power module of claim 10 wherein the signal pins and power pins extend through the encapsulating body.

12. A phase leg for an inverter in an electric vehicle, comprising:
a first insulating substrate having a bonded copper layer on a first side defining circuit traces, a plurality of first signal pins, and a plurality of power terminals, wherein the first signal pins and power terminal are coplanar and each cantilevers beyond an edge of the first substrate;
a plurality of semiconductor chips each containing a respective power transistor and having a respective side soldered to a respective circuit trace on the first substrate that extends to one of the power terminals;
a second insulating substrate parallel to the first substrate and having a bonded copper layer on an interior side facing the first side and defining circuit traces and a plurality of second signal pins, wherein the second signal pins are coplanar and each cantilevers beyond an edge of the second substrate, wherein the circuit traces connect respective power transistors in series with an intermediate junction providing a phase leg output, wherein each chip includes a plurality of signal pads, wherein a first group of the signal pads of each power transistor are each connected to a respective first signal pin, and wherein a second group of the signal pads of each power transistor are each connected to a respective second signal pin;
a plurality of spacers each soldered between the first side and the interior side; and
an encapsulating body securing the substrates, chips, and spacers, wherein the signal pins and power terminals extend through the encapsulating body.

13. The phase leg of claim 12 wherein a pair of the signal pads of each power transistor are adapted to receive a respective gate drive signal, and wherein each first group includes one of the pair of the respective gate drive signal pads and each second group includes the other of the pair of the respective gate drive signal pads.

14. The phase leg of claim 13 wherein respective first and second signal pins connected to each pair of gate drive signal pads are transversely aligned with respect to the edge of the first substrate, whereby a magnetic field associated with a gate current in the respective first and second signal pins is oriented transverse to a magnetic field associated with a switched current in the power terminals.

15. The phase leg of claim 12 wherein a pair of the signal pads of each chip are adapted to provide a chip temperature signal, wherein each first group includes one of the respective pair of temperature signal pads and each second group includes the other of the respective pair of temperature signal pads.

16. The phase leg of claim 15 wherein respective first and second signal pins connected to the respective pair of temperature signal pads are transversely aligned with respect to the edge of the first substrate, whereby a magnetic field associated with a respective temperature signal in the first and second signal pins is oriented transverse to a magnetic field associated with a switched current in the power terminals.

17. The phase leg of claim 12 wherein the first signal pins and the power terminals extend from opposite edges of the first substrate.

18. The phase leg of claim 17 wherein the first and second signal pins extend from proximate edges of the first and second substrates, respectively.

19. The phase leg of claim 12 wherein the first and second substrates each has an exterior side comprised of a bonder copper layer adapted to transfer heat generated in the power transistors.

Assignees

• Ford Global Tech Llc

Inventors

• Xu Fan
• Chen Lihua

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/347

  Dispositions of multiple die-attach connectors · CPC title

• H10W72/07354

  changes in dispositions · CPC title