Signal pin arrangement for multi-device power module
US-10137789-B2 · Nov 27, 2018 · US
Inverter
US2018114740A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018114740-A1 |
| Application number | US-201615334090-A |
| Country | US |
| Kind code | A1 |
| Filing date | Oct 25, 2016 |
| Priority date | Oct 25, 2016 |
| Publication date | Apr 26, 2018 |
| Grant date | — |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.
First claim
Opening claim text (preview).
1 . A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to a transistor gate. 2 . The transistor package of claim 1 , wherein the heat sink comprises fins and contact pads. 3 . The transistor package of claim 1 , further comprising a second transistor that is in series with the first transistor. 4 . The transistor package of claim 3 , wherein the first transistor is an insulated-gate bipolar transistor and the second transistor is a diode transistor. 5 . The transistor package of claim 3 , wherein the first transistor is a metal-oxide-semiconductor-field-effect transistor and the second transistor is a diode transistor. 6 . The transistor package of claim 1 , wherein the transistor package further comprises a copper cladding layer and the Kelvin connection is further connected to a busbar. 7 . The transistor package of claim 1 , wherein the first transistor comprises a gallium nitride or a silicon carbide wideband semiconductor. 8 - 14 . (canceled) 15 . An inverter comprising: a housing, wherein the housing is formed of a metal and is a heat sink; a transistor substrate; an insulated-gate bipolar transistor in thermal contact with the transistor substrate; an encapsulant that at least partially encapsulates the insulated-gate bipolar transistor; and a Kelvin connection to the transistor gate, wherein the transistor substrate is sintered to the housing through a sintered layer. 16 . The inverter of claim 15 , wherein the insulated-gate bipolar transistor comprises gallium nitride or silicon carbide. 17 . The inverter of claim 15 , further comprising a diode transistor in series with the insulated-gate bipolar transistor. 18 . The inverter of claim 15 , wherein the sintered layer comprises silver. 19 . The inverter of claim 15 , wherein the insulated-gate bipolar transistor comprises silicon. 20 . The inverter of claim 15 , wherein the housing comprises fins and contact pads.
Assignees
Inventors
Classifications
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between stacked chips · CPC title
Package configurations · CPC title
Connecting techniques · CPC title
Means for applying energy, e.g. ovens or lasers · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2018114740A1 cover?
- A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.
- Who is the assignee on this patent?
- Tesla Motors Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W40/22. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Apr 26 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).